Pipelined dual port integrated circuit memory

  • US 5,781,480 A
  • Filed: 07/29/1997
  • Issued: 07/14/1998
  • Est. Priority Date: 07/29/1997
  • Status: Expired due to Term
First Claim
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1. An integrated circuit memory, comprising:

  • a plurality of memory cells, each of the plurality of memory cells being coupled to a single word line and to a single bit line pair;

    an address decoder, coupled to the plurality of memory cells, for selecting a memory cell of the plurality of memory cells in response to receiving an address;

    a first address port, coupled to the address decoder, for providing a first address to the address decoder for accessing the plurality of memory cells;

    a second address port, coupled to the address decoder, for providing a second address to the address decoder for accessing the plurality of memory cells;

    a read data port, coupled to the plurality of memory cells, for reading data from the plurality of memory cells in response to either the first or the second address;

    a write data port, coupled to the plurality of memory cells, for writing data to the plurality of memory cells in response to either the first or the second address; and

    a control circuit, coupled to the address decoder, to the first and second address ports, and to the read and write data ports, the control circuit for controlling access to the plurality of memory cells, wherein substantially simultaneous requests for access to the plurality of memory cells are serviced sequentially within a single clock cycle of a clock signal of a data processor accessing the integrated circuit memory.

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