Pipelined dual port integrated circuit memory

• US 5,781,480 A
• Filed: 07/29/1997
• Issued: 07/14/1998
• Est. Priority Date: 07/29/1997
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Nogle, Scott George, Roth, Alan S., Ho, Shuang Li
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US08/902,009
• Time in Patent Office: 350 Days
• Field of Search: 365/189.04, 365/230.05, 365/233, 365/239, 365/154
• US Class Current: 365/189.04
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells, where each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) compares addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

Claims

1. An integrated circuit memory, comprising:

a plurality of memory cells, each of the plurality of memory cells being coupled to a single word line and to a single bit line pair;

an address decoder, coupled to the plurality of memory cells, for selecting a memory cell of the plurality of memory cells in response to receiving an address;

a first address port, coupled to the address decoder, for providing a first address to the address decoder for accessing the plurality of memory cells;

a second address port, coupled to the address decoder, for providing a second address to the address decoder for accessing the plurality of memory cells;

a read data port, coupled to the plurality of memory cells, for reading data from the plurality of memory cells in response to either the first or the second address;

a write data port, coupled to the plurality of memory cells, for writing data to the plurality of memory cells in response to either the first or the second address; and

a control circuit, coupled to the address decoder, to the first and second address ports, and to the read and write data ports, the control circuit for controlling access to the plurality of memory cells, wherein substantially simultaneous requests for access to the plurality of memory cells are serviced sequentially within a single clock cycle of a clock signal of a data processor accessing the integrated circuit memory.

2. The integrated circuit memory of claim 1, wherein the integrated circuit memory is pipelined.

3. The integrated circuit memory of claim 1, further comprising an address collision detector for receiving the first and second addresses, and in response, providing a match signal of a first logic state when the first address is the same as the second address, and for providing the match signal of a second logic state when the first address is not the same as the second address.

4. The integrated circuit memory of claim 3, wherein the match signal is provided to the control circuit to insure that a read access occurs before a write access when the match signal is of the first logic state.

5. The integrated circuit memory of claim 1, wherein the read data port is characterized as being a first read/write data port and the write data port is characterized as being a second read/write data port.

6. The integrated circuit memory of claim 5, further comprising a selfsynchronizing port select circuit, coupled to the first and second read/write data ports, for insuring, on power-up of the integrated circuit memory, that the first address port is synchronized to the first read/write data port and the second address port is synchronized to the second read/write data port.

7. The integrated circuit memory of claim 5, further comprising a passthrough circuit for allowing data that is provided to the first read/write data port to be passed-through to the second read/write data port.

8. The integrated circuit memory of claim 5, wherein the first and second read/write data ports are enabled by first and second externally generated output enable signals, respectively, wherein the first and second externally generated output enable signals are generated independently of any clock signal.

9. A pipelined dual port static random access memory, comprising:

a plurality of static random access memory cells, each of the plurality of static random access memory cells being coupled to a single word line and to a single bit line pair;

an address decoder, coupled to the plurality of static random access memory cells, for selecting a memory cell of the plurality of static random access memory cells in response to receiving an address;

a first address port, coupled to the address decoder, for providing a first address to the address decoder for accessing the plurality of static random access memory cells;

a second address port, coupled to the address decoder, for providing a second address to the address decoder for accessing the plurality of static random access memory cells;

a first read/write data port, coupled to the plurality of static random access memory cells, for reading data from the plurality of static random access memory cells in response to either the first address or the second address;

a second read/write data port, coupled to the plurality of memory cells, for writing data to the plurality of static random access memory cells in response to either the first or the second address; and

a control circuit, coupled to the address decoder, to the first and second address ports, and to the first and second read/write data ports, the control circuit for controlling access to the plurality of static random access memory cells, wherein substantially simultaneous requests for access to the plurality of static random access memory are serviced sequentially within a single clock cycle of a clock signal of a data processor accessing the pipelined dual port static random access memory.

10. The pipelined dual port static random access memory of claim 9, further comprising an address collision detector for receiving the first and second addresses, and in response, providing a match signal of a first logic state when the first address is the same as the second address, and for providing the match signal of a second logic state when the first address is not the same as the second address.

11. The pipelined dual port static random access memory of claim 10, wherein the match signal is provided to the control circuit to insure that a read access occurs before a write access when the match signal is of the first logic state.

12. The pipelined dual port static random access memory of claim 9, further comprising a self-synchronizing port select circuit, coupled to the first and second read/write data ports, for insuring, on power-up of the pipelined dual-port static random access memory, that the first address port is synchronized to the first read/write data port and the second address port is synchronized to the second read/write data port.

13. The pipelined dual port static random access memory of claim 9, further comprising a pass-through circuit for allowing data that is provided to the first read/write data port to be passed-through to the second read/write data port.

14. The pipelined dual port static random access memory of claim 9, wherein the first and second read/write data ports are enabled by first and second externally generated output enable signals, respectively, wherein the first and second externally generated output enable signals are generated independently of any clock signal.

15. A pipelined dual port static random access memory, comprising:

a plurality of static random access memory cells, each of the plurality of static random access memory cells being coupled to a single word line and to a single bit line pair;

an address decoder, coupled to the plurality of static random access memory cells, for selecting a memory cell of the plurality of static random access memory cells in response to receiving an address;

a first address port, coupled to the address decoder, for providing a first address to the address decoder for accessing the plurality of static random access memory cells;

a second address port, coupled to the address decoder, for providing a second address to the address decoder for accessing the plurality of static random access memory cells;

an address collision detector, coupled to the first and second address ports, for receiving the first and second addresses, and in response, providing a match signal of a first logic state when the first address is the same as the second address, and for providing the match signal of a second logic state when the first address is not the same as the second address;

a first read/write data port, coupled to the plurality of static random access memory cells, for reading data from the plurality of static random access memory cells in response to either the first address or the second address;

a second read/write data port, coupled to the plurality of static random access memory cells, for writing data to the plurality of static random access memory cells in response to either the first address or the second address; and

a control circuit, coupled to the address decoder, to the first and second address ports, to the address collision detector, and to the first and second read/write data ports, the control circuit for controlling access to the plurality of memory cells wherein substantially simultaneous requests for access to the plurality of static random access memory cells are serviced sequentially within a single clock cycle of a clock signal of a data processor that is accessing the pipelined dual-port static random access memory, and wherein the match signal determines which of the first and second read/write data ports are serviced first.

16. The pipelined dual port static random access memory of claim 15, wherein the match signal is provided to the control circuit to insure that a read access occurs before a write access when the match signal is of the first logic state.

17. The pipelined dual port static random access memory of claim 15, further comprising a self-synchronizing port select circuit, coupled to the first and second read/write data ports, for insuring, on power-up of the pipelined dual-port static random access memory, that the first address port is synchronized to the first read/write data port and the second address port is synchronized to the second read/write data port.

18. The pipelined dual port static random access memory of claim 15, further comprising a pass-through circuit, coupled to the first and second read/write data ports, for allowing data that is provided to the first read/write data port to be passed-through to the second read/write data port.

19. The pipelined dual port static random access memory of claim 15, wherein the first and second read/write data ports are enabled by first and second externally generated output enable signals, respectively, wherein the first and second externally generated output enable signals are generated independently of any clock signal.