Random access memory word line select circuit having rapid dynamic deselect

  • US 5,781,497 A
  • Filed: 08/02/1996
  • Issued: 07/14/1998
  • Est. Priority Date: 08/02/1996
  • Status: Expired due to Term
First Claim
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1. In a random access memory having at least one array of memory cells, a word line driver circuit, comprising:

  • a plurality of word lines;

    a driver stage coupled to each word line, each driver stage including a first transistor of a first conductivity type having a source-drain path coupled between a word line and a first voltage and a second transistor of a second conductivity type having a source-drain path coupled between the word line and a reference voltage, the control gates of the first and second transistors being commonly coupled to a drive node;

    a select circuit includinga passgate transistor associated with each drive stage, each passgate transistor having a source-drain path coupled between the drive node of its associated driver stage and a decode node, anda pre-charge circuit coupled between the decode node and a second voltage, the second voltage being less than the first voltage,said select circuit being responsive to at least one decode signal; and

    a dynamic de-select circuit including a pull-up circuit coupled between the drive node and the first voltage and responsive to a first control signal.

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