Dynamic power management of solid state memories

• US 5,781,784 A
• Filed: 08/25/1997
• Issued: 07/14/1998
• Est. Priority Date: 07/09/1992
• Status: Expired due to Term

• Current Assignee: Acacia Patent Acquisition LLC (Acacia Research Corporation)
• Original Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Inventors: McKinley, David E.
• Primary Examiner(s): Davis, George B.
• Application Number:
  US08/918,745
• Time in Patent Office: 323 Days
• Field of Search: 395/750.03, 395/750.01, 364/707, 365/227, 365/228, 365/229
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A dynamic power management device for supplying power to a solid state memory integrated circuit includes power control circuitry for supplying a variable voltage to the memory integrated circuit and logic control circuitry responsive to data access activity for generating address and control signals for the memory integrated circuit and for controlling the power control circuitry to supply power to the memory integrated circuit sufficient to maintain memory information in the memory integrated circuit during periods of no data access activity and sufficient to exchange memory information with the memory integrated circuit during periods of data access activity. Power consumption of the memory integrated circuit is thereby curtailed.

Claims

1. A dynamic power management device for supplying power to a solid state memory integrated circuit, said device comprising:

power control means for supplying a variable voltage to said memory integrated circuit; and

logic control means for generating address and control signals for said memory integrated circuit and for controlling said power control means;

wherein the power control means supply power to said memory integrated circuit, said power being supplied to the memory integrated circuit at a first variable voltage level during periods of no data access activity and at a second variable voltage level during periods of data access activity, the variable voltage supplied at said first variable voltage level being less than the variable voltage supplied at said second variable voltage level,

wherein the power supplied at the first level is sufficient to preserve information stored in the integrated memory circuit and the power supplied at the second level is sufficient to read and write information in the integrated memory circuit.

2. The dynamic power management device of claim 1, further comprising I/O means for converting parallel data signals to serial data signals for input to said memory integrated circuit and for converting data signals output from said memory integrated circuit from serial to parallel.

3. The dynamic sower management device of claim 2, wherein said power control means comprises means for selecting between alternate power sources, and means for feeding voltage information back to said logic control means.

4. The dynamic power management device of claim 3, wherein said voltage information includes both voltage output information used by said logic control means to cause said power control means to maintain a specified voltage output and voltage source information used by said logic control means to cause said means for selecting to select one of said alternate power sources.

5. The dynamic power management device of claim 4, wherein said power control means comprises a pulse width modulator circuits said logic control means causing said pulse width modulator circuit to generate a pulse width modulated signal having pulses with pulse widths proportional to said specified voltage output.

6. The dynamic power management device of claim 5, wherein said power control means further comprises a low pass filter, said low pass filter filtering said pulse width modulated signal.

7. The dynamic power management device of claim 6, wherein said power control means further comprises a FET driver circuit coupled to said pulse width modulator circuit, said FET driver circuit generating a variable voltage having a voltage level proportional to the pulse widths of pulses in said filtered pulse width modulated signal.

8. The dynamic power management device of claim 4, wherein said logic control means controls said power control means to maintain said specified voltage output through closed loop monitoring of said voltage output information.

9. The dynamic power management device of claim 3, wherein said logic control means generates said control signals for data access activity when said power control means supplies a voltage high enough to perform the data access activity and does not generate said control signals for data access activity when said power supply means does not supply a voltage high enough to perform the data access activity.

10. The dynamic power management device of claim 2, wherein said logic control means comprises a DNA controller, a data sequencer, and a timing sequencer.

11. The dynamic power management device of claim 10, wherein said logic control means further comprises refresh timer means for timing refresh intervals, a binary address generator, and an encoder, said logic control means generating said address signals for said memory integrated circuit.

12. The dynamic power management device of claim 11, wherein said encoder is a Gray code encoder.

13. The dynamic power management device of claim 2, further comprising slew rate controller means for limiting the time rate of change of voltage of said control signals and said data signals transmitted to said memory integrated circuit.

14. The dynamic power management device of claim 2, wherein said periods of data access activity include memory access periods and memory refresh periods, wherein said periods of no data access activity include standby periods including periods between refresh periods and wherein said logic control means causes said power control means to supply to said integrated circuit a relatively low value of said voltage during said standby periods, a higher value of said voltage during said memory refresh periods, and a still higher value of said voltage during said memory access periods.

15. The dynamic power management device of claim 2, further comprising daisy chain controller means for enabling communication with another dynamic power management device.

16. The dynamic power management device of claim 2, wherein said logic control means is provided with a sleep mode for conserving power during periods of inactivity.

17. The dynamic power management device of claim 2, wherein said I/O means further comprises error correction means for detecting and correcting errors in said parallel data signals.

18. The dynamic power management device of claim 1, wherein said power control means further comprises an internal voltage generator, said internal voltage generator generating a calibration voltage.

19. The dynamic power management device of claim 1, wherein said dynamic power management device supplies power to a plurality of memory integrated circuits in said computer system.

20. The dynamic power management device of claim 19, wherein said dynamic power management device further comprises a plurality of ports, each port of said plurality of ports coupled to one memory integrated circuit of said plurality of memory integrated circuits.

21. An integrated circuit for controlling a level of power supplied to a solid state memory integrated circuit having a first operation period for maintaining information stored in said memory integrated circuit, a second operation period for refreshing data stored in said memory integrated circuit, and a third operation period for accessing said memory integrated circuit, said memory integrated circuit having a first voltage requirement during said first operational period, a second voltage requirement during said second operational period and a third voltage requirement during said third operational period, said integrated circuit comprising:

power control means for supplying a variable voltage to said memory integrated circuit; and

logic control means for causing said power control means to supply to said memory integrated circuit a first voltage during said first operation period, a second voltage different from said first voltage during said second operation period, and a third voltage different from said first and second voltages during said third operation period.

22. The integrated circuit of claim 21, wherein said logic control means causes said memory integrated circuit to enter said first, second or third operation period only when said power control means supplies a voltage meeting the voltage requirements of said memory integrated circuit to enter said first, second or third operation period, respectively.

23. A dynamic power management device for supplying power to a solid state memory integrated circuit in a computer system having a power source supplying a substantially constant voltage, said dynamic power management device comprising:

power control means coupled to said power source for supplying a variable voltage to said memory integrated circuit, said variable voltage being less than or equal to said substantially constant voltage supplied by said power source; and

logic control means for generating address and control signals for said memory integrated circuit and for controlling said power control means;

wherein the power control means supply power to said memory integrated circuit, said power being supplied to the memory integrated circuit at a first variable voltage level during periods of no data access activity and at a second variable voltage level during periods of data access activity, the variable voltage supplied at said first variable voltage level being less than the variable voltage supplied at said second variable voltage level,

wherein the power supplied at the first level is sufficient to preserve information stored in the integrated memory circuit and the power supplied at the second level is sufficient to read and write information in the integrated memory circuit.