Power saving PLL circuit
First Claim
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1. A phase lock loop comprising:
- a voltage controlled oscillator section for receiving a first signal representing a control voltage to output a second signal having a first frequency based on the control voltage;
a phase comparator for comparing a first phase of the second signal against a second phase of a reference signal having a reference frequency to output a first or second phase error signal representing a magnitude of a phase lead or phase lag of the first phase with respect to the second phase;
a current controller for receiving the first and second phase error signals to output a current control signal representing a magnitude of the phase lead or phase lag, the current control signal being represented by n bits wherein n is not lower than two; and
a control voltage generating section for receiving the first and second phase error signals and current control signal to generate the first signal based on the current control signal.
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Abstract
A phase lock loop includes a voltage controlled oscillator (VCO), a phase comparator for comparing the phases of the output of the VCO and a reference signal, a charge pump circuit, including a plurality of current sources, for supplying a control voltage by charging or discharging a capacitor based on the outputs of the current sources, and a current source controller for controlling the current output of the current sources by a n-bit current control signal. Charge current and discharge current by the charge pump circuit are controlled in n bits so that a rapid synchronization during lock-in and a low jitter after lock-in can be obtained.
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9 Claims
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1. A phase lock loop comprising:
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a voltage controlled oscillator section for receiving a first signal representing a control voltage to output a second signal having a first frequency based on the control voltage; a phase comparator for comparing a first phase of the second signal against a second phase of a reference signal having a reference frequency to output a first or second phase error signal representing a magnitude of a phase lead or phase lag of the first phase with respect to the second phase; a current controller for receiving the first and second phase error signals to output a current control signal representing a magnitude of the phase lead or phase lag, the current control signal being represented by n bits wherein n is not lower than two; and a control voltage generating section for receiving the first and second phase error signals and current control signal to generate the first signal based on the current control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification