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Power saving PLL circuit

  • US 5,783,972 A
  • Filed: 11/27/1996
  • Issued: 07/21/1998
  • Est. Priority Date: 11/29/1995
  • Status: Expired due to Fees
First Claim
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1. A phase lock loop comprising:

  • a voltage controlled oscillator section for receiving a first signal representing a control voltage to output a second signal having a first frequency based on the control voltage;

    a phase comparator for comparing a first phase of the second signal against a second phase of a reference signal having a reference frequency to output a first or second phase error signal representing a magnitude of a phase lead or phase lag of the first phase with respect to the second phase;

    a current controller for receiving the first and second phase error signals to output a current control signal representing a magnitude of the phase lead or phase lag, the current control signal being represented by n bits wherein n is not lower than two; and

    a control voltage generating section for receiving the first and second phase error signals and current control signal to generate the first signal based on the current control signal.

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