Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation
First Claim
1. A method of preventing information corruption in a cache memory due to a bus error which occurs during a linefill operation, said method comprising the steps of:
- providing a tag in association with each cache line of said cache memory;
validating a tag associated with a particular cache line to indicate said particular cache line is valid before a linefill operation is performed to said particular cache line; and
in response to an occurrence of a bus error during said linefill operation, invalidating said tag associated with said particular cache line to indicate said particular cache line is invalid, such that the integrity of information within said particular cache line is maintained.
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Accused Products
Abstract
A method and system for preventing information corruption in a cache memory due to a bus error which occurs during a cache linefill operation is disclosed. The cache memory includes multiple cache lines, and a tag is associated with each cache line. In accordance with the present disclosure, a tag associated with a cache line is validated before a linefill operation is performed on the cache line. In response to an occurrence of a bus error during the linefill operation, the tag associated with the cache line for which a linefill operation is performed, is invalidated such that the information within the cache line remains valid during a linefill operation unless a bus error occurs.
19 Citations
11 Claims
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1. A method of preventing information corruption in a cache memory due to a bus error which occurs during a linefill operation, said method comprising the steps of:
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providing a tag in association with each cache line of said cache memory; validating a tag associated with a particular cache line to indicate said particular cache line is valid before a linefill operation is performed to said particular cache line; and in response to an occurrence of a bus error during said linefill operation, invalidating said tag associated with said particular cache line to indicate said particular cache line is invalid, such that the integrity of information within said particular cache line is maintained. - View Dependent Claims (2, 3, 4)
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5. A cache memory having a mechanism for preventing information corruption due to a bus error which occurs during a linefill operation, said cache memory comprising:
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a plurality of cache lines having a tag associated with each of said plurality of caches lines; means for validating a tag associated with a particular cache line to indicate said particular cache line is valid before a linefill operation is performed to said particular cache line; and means for invalidating said tag associated with said particular cache line to indicate said particular cache line is invalid, in response to an occurrence of a bus error during said linefill operation. - View Dependent Claims (6, 7, 8)
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9. A data processing system having a mechanism for preventing information corruption due to a bus error which occurs during a linefill operation, said data processing system comprising:
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a processor; a cache memory within said processor, wherein said cache memory includes a plurality of cache lines having a tag associated with each of said plurality of cache lines; means for validating a tag associated with a particular cache line to indicate said particular cache line is valid before a linefill operation is performed to said particular cache line; and means for invalidating said tag associated with said particular cache line to indicate said particular cache line is invalid, in response to an occurrence of a bus error during said linefill operation. - View Dependent Claims (10, 11)
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Specification