Signal processing system
First Claim
1. A circuit for processing modulated signals, comprising a semiconductor integrated carrier recovery circuit operative to control a demodulator, comprising:
- a numerically controlled oscillator;
a digital derotation circuit responsive to said numerically controlled oscillator and accepting an in phase component and a quadrature component of sampled signals;
an adaptive phase error estimation circuit, coupled to an output of said derotation circuit, wherein said adaptive phase error estimation circuit error executes a least-mean-square algorithm and comprises;
first and second slicers, accepting a derotated in-phase value and a derotated quadrature value respectively;
first and second subtracters, for respectively determining first and second differences between said derotated in phase value and said sliced in phase value, and between said derotated quadrature value and said sliced quadrature value; and
an angulator, accepting said first and second differences and outputting a phase error estimate; and
a loop filter coupled to an output of said adaptive phase error estimation circuit;
wherein said numerically controlled oscillator is responsive to said loop filter.
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Accused Products
Abstract
A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery, having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.
218 Citations
23 Claims
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1. A circuit for processing modulated signals, comprising a semiconductor integrated carrier recovery circuit operative to control a demodulator, comprising:
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a numerically controlled oscillator; a digital derotation circuit responsive to said numerically controlled oscillator and accepting an in phase component and a quadrature component of sampled signals; an adaptive phase error estimation circuit, coupled to an output of said derotation circuit, wherein said adaptive phase error estimation circuit error executes a least-mean-square algorithm and comprises; first and second slicers, accepting a derotated in-phase value and a derotated quadrature value respectively; first and second subtracters, for respectively determining first and second differences between said derotated in phase value and said sliced in phase value, and between said derotated quadrature value and said sliced quadrature value; and
an angulator, accepting said first and second differences and outputting a phase error estimate; anda loop filter coupled to an output of said adaptive phase error estimation circuit;
wherein said numerically controlled oscillator is responsive to said loop filter. - View Dependent Claims (2)
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3. A signal processing apparatus for processing modulated signals that have a modulation carrier frequency, the apparatus comprising:
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a demodulator; a sampler operative at a sampling rate on an output of said demodulator; and a carrier recovery circuit operative to control said demodulator in accordance with said modulation carrier frequency, the circuit comprising; a numerically controlled oscillator; a digital derotation circuit responsive to said numerically controlled oscillator and accepting an in phase component and a quadrature component of sampled signals; a phase error estimation circuit, coupled to an output of said derotation circuit; and a loop filter coupled to an output of said phase error estimation circuit; wherein said numerically controlled oscillator is responsive to said loop filter; a circuit for adaptively estimating the phase error;
comprising means for executing a least-mean-square algorithm, and further comprising;first and second slicers, accepting a derotated in-phase value and a derotated quadrature value respectively; first and second subtracters, for respectively determining first and second differences between said derotated in phase value and said sliced in phase value, and between said derotated quadrature value and said sliced quadrature value; and an angulator, accepting said first and second differences and outputting a phase error estimate; wherein said sampler and said carrier recovery circuit are integrated in a semiconductor integrated circuit. - View Dependent Claims (4)
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5. A signal processing apparatus for processing modulated signals that are sampled by a sampler operative at a sampling rate, the signals having a transmitted symbol rate, the apparatus comprising:
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a first numerically controlled oscillator operative at periods T; a sinc interpolator receiving samples at said sampling rate; a first loop filter, coupled to said sinc interpolator and said first numerically controlled oscillator having an output responsive to a difference between said periods T and said transmitted symbol rate of said sampled signals;
wherein said first numerically controlled oscillator is responsive to said first loop filter and generates an output signal that is representative of an interpolation distance between succeeding samples, and said sinc interpolator interpolates said received samples according to said interpolation distance, and produces an output signal representative of said interpolated samples; anda carrier recovery circuit, comprising; a second numerically controlled oscillator; a digital derotation circuit responsive to said second numerically controlled oscillator and accepting an in phase component and a quadrature component of sampled signals; a phase error estimation circuit, coupled to an output of said derotation circuit; and a loop filter coupled to an output of said phase error estimation circuit; wherein said second numerically controlled oscillator is responsive to said loop filter;
wherein said first and second numerically controlled oscillators, said sinc interpolator, said first and second loop filters, and said digital derotation circuit are integrated in a semiconductor integrated circuit. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A circuit for processing modulated signals, comprising a semiconductor integrated carrier recovery circuit operative to control a demodulator, comprising:
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an adaptive phase error estimation circuit executing a least-mean-square algorithm and comprising; first and second slicers, accepting a derotated in-phase value and a derotated quadrature value respectively; first and second subtracters, for respectively determining first and second differences between said derotated in phase value and said sliced in phase value, and between said derotated quadrature value and said sliced quadrature value; and an angulator, accepting said first and second differences and outputting a phase error estimate; and a digital derotation circuit responsive to said phase error estimation circuit, and accepting an in phase component and a quadrature component of sampled signals. - View Dependent Claims (23)
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Specification