General purpose, multiple precision parallel operation, programmable media processor

• US 5,794,061 A
• Filed: 11/22/1996
• Issued: 08/11/1998
• Est. Priority Date: 08/16/1995
• Status: Expired due to Term

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): SHAH, ALPESH
• Application Number:
  US08/754,829
• Time in Patent Office: 627 Days
• Field of Search: 395/800.01, 395/670, 395/376, 395/280, 364/131-134, 364/736, 364/741, 364/745, 364/748, 364/754, 364/761, 364/768, 364/736.01, 364/745.01, 364/748.01, 364/754.01
• US Class Current: 712/1
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/238 : Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams hybrid fiber coaxial [HFC] networks for downstream channel allocation for video distribution H04L12/2801; flow control in packet networks H04L47/10; real-time communication protocols in data switching networks H04L65/00; scheduling or organising the servicing of application requests H04L67/60
• CPC Class Codes: H04N 21/23805 : Controlling the feeding rate to the network, e.g. by controlling the video pump
• CPC Class Codes: H04N 21/4347 : Demultiplexing of several video streams
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor. The general purpose, programmable media processor is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams. Parallel general purpose media processors are disposed throughout the network in a distributed virtual manner to allow for multi-processor operations and sharing of resources through the network. A method for receiving, processing and transmitting media data streams over the communications fabric is also provided.

Claims

1. A general purpose programmable media processor having an instruction path and a data path to digitally process a plurality of media data streams, comprising:

a high bandwidth external interface operable to receive a plurality of data of various sizes from an external source and communicate the received data over the data path at a rate that maintains substantially peak operation of the media processor;

at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and

a multi-precision execution unit coupled to the data path, the multi-precision execution unit configurable to dynamically partition data received from the data path to account for the elemental symbol width of the plurality of media data streams, said elemental symbol width being equal to or narrower than the data path, and programmable to operate on the data to generate a unified symbol output to the data path.

2. The media processor defined in claim 1, wherein the execution unit is dynamically configurable to partition data received from the data path.

3. The media processor defined in claim 1, further comprising:

means for moving data between registers and memory by performing load and store operations, and for coordinating the sharing of data among a plurality of tasks by performing synchronization operations based upon instructions and data received by the execution unit;

means for securely controlling the sequence of execution by performing branch and gateway operations based upon instructions and data received by the execution unit; and

a memory management unit, the memory management unit operable to retrieve data and instructions for timely and secure communication over the data path and instruction path.

4. The media processor defined in claim 3, further comprising:

a combined instruction cache and buffer, the combined instruction cache and buffer dynamically allocated between cache space and buffer space to ensure real-time execution of multiple media instruction streams; and

a combined data cache and buffer, the combined data cache and buffer dynamically allocated between cache space and buffer space to ensure real-time response for multiple media data streams.

5. The media processor defined in claim 4, wherein real-time execution is ensured by dynamically allocating instruction buffer space to the smallest and most frequently executed blocks of media instructions.

6. The media processor defined in claim 4, wherein real-time response is ensured by dynamically allocating data buffer space to the smallest and most frequently accessed working sets of media data.

7. The media processor defined in claim 1, wherein media data streams comprise Nyquist sampled inputs and outputs.

8. The media processor defined in claim 1, wherein media data streams originate from standard computer memory and I/O interfaces.

9. The media processor defined in claim 1, wherein the multi-precision execution unit is configurable to divide the data into component symbols of various sizes, analyze the component symbols based upon instructions, and resynthesize the component symbols for communication over the data path.

10. The media processor defined in claim 1, wherein the plurality of media data streams comprise presentation media information, transmission media information, and storage media information.

11. The media processor defined in claim 10, wherein presentation media information comprises audio, video, image, and graphical information.

12. The media processor defined in claim 10, wherein transmission media information comprises radio and network data transmissions.

13. The media processor defined in claim 10, wherein storage media information comprises data encoded in moving and solid-state memory media.

14. The media processor defined in claim 1, wherein the width of the data path is at least 128 bits.

15. The media processor defined in claim 1, wherein the multi-precision execution unit comprises a dynamically partitionable arithmetic unit, a register controllable cross-bar switch, and an extended mathematical element.

16. The media processor defined in claim 13, wherein the register controllable cross-bar switch comprises a Benes network design.

17. The media processor defined in claim 15, wherein the register controllable cross-bar switch is programmable and is operable to manipulate symbols.

18. The media processor defined in claim 11, wherein the extended mathematical element is operable to perform finite group, finite field, finite ring and table look-up operations on the symbols.

19. The media processor defined in claim 1, further comprising a set of predefined instructions accessible by a user.

20. The media processor defined in claim 2, wherein the means for performing load, store, and synchronization operations and the means for performing branch and gateway operations comprises a set of predefined instructions accessible by a user.

21. The media processor defined in claim 20, wherein the predefined instructions are combinable to implement composite functions on the plurality of media data streams.

22. A parallel multi-processor system that maintains substantially peak data throughput in the unified execution of a plurality media data streams, the system having a data path, comprising:

at least one high bandwidth external interface, the at least one high bandwidth external interface coupled to the data path and operable to receive a plurality of data of various sizes from an external source and communicate the received data over the data path at a rate that maintains substantially peak operation of the parallel multi-processor system;

a plurality of register files, each register file having at least one general purpose register coupled to the data path and operable to store a working set of media data received from the data path and to communicate the stored data to the data path; and

at least one multi-precision execution unit coupled to the data path, the at least one multi-precision execution unit configurable to dynamically partition data within the working set of media data received from the data path to account for the elemental symbol width of the plurality of media data streams, said elemental symbol width being equal to or narrower than the data path, and programmable to operate in parallel on the dynamically partitioned data to generate a unified symbol output for each register file.

23. The parallel multi-processor system defined in claim 22, wherein the at least one execution unit alternates in a round robin manner to operate on data stored in the plurality of register files.

24. The parallel multi-processor system defined in claim 22, further comprising an instruction pre-fetch pipeline.

25. The parallel multi-processor system defined in claim 24, wherein the instruction pre-fetch pipeline comprises a super-string pipeline.

26. The parallel multi-processor system defined in claim 24, wherein the instruction pre-fetch pipeline comprises a super-spring pipeline.

27. The parallel multi-processor system defined in claim 22, further comprising a data pre-fetch pipeline.

28. The parallel multi-processor system defined in claim 27, wherein the data pre-fetch pipeline comprises a super-string pipeline.

29. The parallel multi-processor system defined in claim 27, wherein the data pre-fetch pipeline comprises a super-spring pipeline.

30. The parallel multi-processor system defined in claim 22, further comprising a requester, responder and transponder daemon.