Thin film transistors fabricated on plastic substrates

• US 5,796,121 A
• Filed: 03/25/1997
• Issued: 08/18/1998
• Est. Priority Date: 03/25/1997
• Status: Expired due to Term

• Current Assignee: AU Optronics Corporation, Merck & Co., Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Gates, Stephen McConnell
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/823,844
• Time in Patent Office: 511 Days
• Field of Search: 257/59, 257/60, 257/72, 257/506, 257/40
• US Class Current: 257/59
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

A thin film transistor is described incorporating a gate electrode, a gate insulating layer, a semiconducting channel layer deposited on top of the gate insulating layer, an insulating encapsulation layer positioned on the channel layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer, all of which are situated on a plastic substrate. By enabling the use of plastics having low glass transition temperatures as substrates, the thin film transistors may be used in large area electronics such as information displays and light sensitive arrays for imaging which are flexible, lighter in weight and more impact resistant than displays fabricated on traditional glass substrates. The thin film transistors are useful in active matrix liquid crystal displays where the plastic substrates are transparent in the visible spectrum. Enablement of the use of such plastics is by way of the use of polymeric encapsulation films to coat the surfaces of the plastic substrates prior to subsequent processing and the use of novel low temperature processes for the deposition of thin film transistor structures.

Claims

1. A thin film transistor comprising:

a) a substrate,

b) a polymeric encapsulation film which covers said substrate,

c) a gate electrode,

d) a gate insulating layer,

e) a semiconducting channel layer deposited on top of said gate insulating layer,

f) an insulating encapsulation layer positioned on said channel layer,

g) a source electrode,

h) a drain electrode, and

i) a contact layer situated beneath each of said source and drain electrodes and in contact with at least said channel layer

wherein said substrate is a plastic having a low glass transition temperature.

2. The thin film transistor of claim 1 wherein said gate electrode is a metal.

3. The thin film transistor of claim 2 wherein said metal is one selected from the group comprising chromium, tantalum, molybdenum, tungsten, copper and alloys thereof.

4. The thin film transistor of claim 1 wherein said gate electrode is a tri-layer selected from the group comprising chromium/M/chromium and Ti/M/Ti where M is a metal selected from the group comprising chromium, tantalum, molybdenum, tungsten, copper and alloys thereof.

5. The thin film transistor of claim 1 wherein said gate dielectric is amorphous SiNitride.

6. The thin film transistor of claim 1 wherein said channel layer is amorphous silicon.

7. The thin film transistor of claim 1 wherein said insulating encapsulation layer is amorphous SiNitride.

8. The thin film transistor of claim 1 wherein said contact layer is an n-type semiconductor.

9. The thin film transistor of claim 8 wherein said n-type semiconductor is a-Si:

H doped with phosphorus.

10. The thin film transistor of claim 1 wherein said contact layer is a low work function metal.

11. The thin film transistor of claim 1 further including a passivation layer over the top of said thin film transistor.

12. A planar array comprising a plurality of claim 1 thin film transistors.

13. A thin film transistor comprising:

a) a substrate,

b) a polymeric encapsulation film which covers said substrate,

c) a gate electrode,

d) a gate insulating layer,

e) a semiconducting channel layer deposited on top of said gate insulating layer,

f) a contact layer positioned over said channel layer and being discontinuous such that said contact layer consists of two sections,

g) a source electrode in contact with one of said two sections of said contact layer,

h) a drain electrode in contact with the other of said two sections of said contact layer, and

i) an insulating encapsulation layer in contact with at least a part of said source electrode, said drain electrode, said channel layer and said contact layers,

wherein said substrate is a plastic having a low glass transition temperature.

14. The thin film transistor of claim 13 wherein said gate electrode is a metal.

15. The thin film transistor of claim 14 wherein said metal is one selected from the group comprising chromium, tantalum, molybdenum, tungsten, copper and alloys thereof.

16. The thin film transistor of claim 13 wherein said gate electrode is a tri-layer selected from the group comprising chromium/M/chromium and Ti/M/Ti where M is a metal selected from the group comprising chromium, tantalum, molybdenum, tungsten, copper and alloys thereof.

17. The thin film transistor of claim 13 wherein said gate dielectric is amorphous SiNitride.

18. The thin film transistor of claim 13 wherein said channel layer is amorphous silicon.

19. The thin film transistor of claim 13 wherein said insulating encapsulation layer is SiNitride.

20. The thin film transistor of claim 13 wherein said contact layer is an n-type semiconductor.

21. The thin film transistor of claim 20 wherein said n-type semiconductor is a-Si:

H doped with phosphorus.

22. The thin film transistor of claim 13 wherein said contact layer is a low work function metal.

23. The thin film transistor of claim 13 further including a passivation layer over the top of said thin film transistor.

24. A planar array comprising a plurality of claim 13 thin film transistors.

25. A thin film transistor comprising:

a) a substrate,

b) a polymeric encapsulation film which covers said substrate,

c) a conducting gate layer,

d) a protective layer over the top of said gate metal layer,

e) a gate insulating layer,

f) a semiconducting channel layer deposited on top of said gate insulating layer,

g) an insulating encapsulation layer positioned on said channel layer said layer having two apertures therein,

h) a thin semiconductor layer positioned in each of said apertures and over a part of the top of said insulating encapsulation layer and coating the walls of said apertures and contacting said channel layer,

i) a source electrode consisting of a conducting polymer deposited in one of said apertures and in contact with said thin contact layer, and

j) a drain electrode consisting of a conducting polymer deposited in the other of said apertures and in contact with said thin semiconductor layer,

wherein said substrate is a plastic having a low glass transition temperature.

26. The thin film transistor of claim 25 wherein said gate layer is a conducting polymer.

27. The thin film transistor of claim 26 wherein said conducting polymer is one selected from the group consisting of polyaniline, polyacetylene and polyphenylenevinylene.

28. The thin film transistor of claim 25 wherein said protective layer is a doped layer of n-type a-Si:

H.

29. The thin film transistor of claim 25 wherein said protective layer is chromium.

30. The thin film transistor of claim 25 wherein said gate dielectric is amorphous SiNitride.

31. The thin film transistor of claim 25 wherein said channel layer is amorphous silicon.

32. The thin film transistor of claim 25 wherein said insulating encapsulation layer is amorphous SiNitride.

33. The thin film transistor of claim 25 wherein said contact layer is an n-type semiconductor.

34. The thin film transistor of claim 33 wherein said n-type semiconductor is a-Si:

H doped with phosphorus.

35. The thin film transistor of claim 25 wherein said contact layer is a low work function metal.

36. The thin film transistor of claim 25 wherein the conducting polymer of said source electrode and said drain electrode is one selected from the group consisting of polyaniline, polyacetylene and polyphenylenevinylene.

37. The thin film transistor of claim 25 further including a passivation layer over the top of said thin film transistor.

38. A planar array comprising a plurality of claim 25 thin film transistors.