Inductance reduced wire-bonding type semiconductor device

• US 5,798,571 A
• Filed: 07/02/1996
• Issued: 08/25/1998
• Est. Priority Date: 07/04/1995
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakajima, Hirofumi
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US08/674,721
• Time in Patent Office: 784 Days
• Field of Search: 257/748, 257/691, 257/666, 257/698, 257/676, 257/678, 257/692, 257/697, 257/690, 257/773, 257/786, 257/784, 257/782, 257/776
• US Class Current: 257/784
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

The invention provides a wire-bonding type semiconductor device including, a semiconductor chip, a plurality sets of electrode pads formed on the semiconductor chip, each set including a power supply electrode, at least one signal electrode pad and a gland electrode pad arranged in this order, a mount on which the semiconductor chip is placed, the mount being formed with the same number of extensions as the number of the gland electrode pads, the extension acting as gland leads, the same number of power supply leads as the number of the power supply electrode pads, the same number of signal leads as the number of the signal electrode pads, the power supply leads, the signal leads and the projections acting as gland leads being arranged in this order, and metal wires for connecting each of the power supply electrode pads, signal electrode pads and gland electrode pads to the power supply leads, the signal leads and the extensions, respectively, the metal wires being disposed substantially in parallel with one another and having substantially the same length. The invention makes it possible to remarkably reduce effective inductance of thin metal wires, and thus provides a high-speed operable semiconductor device which can be fabricated by conventional wire-bonding techniques and has significantly low gland bounce noise and cross-talk which would be caused by concurrent switching.

Claims

1. A wire-bonding type semiconductor device comprising:

a semiconductor chip;

a plurality of power supply electrode pads formed on said semiconductor chip;

a plurality of signal electrode pads formed on said semiconductor chip;

a plurality of ground electrode pads formed on said semiconductor chip;

a plurality of first thin metal wires for electrically connecting said power supply electrode pads to associated internal terminals of a package;

a plurality of second thin metal wires for electrically connecting said signal electrode pads to associated internal terminals of a package; and

a plurality of third thin metal wires for electrically connecting said ground electrode pads to associated internal terminals of a package;

said power supply electrode pads, said signal electrode pads and said ground electrode pads being arranged in sets on said semiconductor chip so that each set includes at least one signal electrode pad being always disposed intermediate between a power supply electrode pad and a ground electrode pad, and the distance between said sets is larger than the distance between the power supply electrode pads, signal electrode pads, and ground electrode pads in each set, and

said first, second and third thin metal wires are designed so that a first thin metal wire, a third thin metal wire and at least one second thin metal wire located intermediate between said first and third thin metal wires are disposed substantially in parallel with one another and have substantially the same length.

2. The wire-bonding type semiconductor device as set forth in claim 1, wherein wires leading from said power supply electrode pads and said ground electrode pads to said associated internal terminals of a package, route to external terminals which are provided so that the number of power supply external terminals and ground external terminals is smaller than the number of said power supply electrode pads and ground electrode pads.

3. The wire-bonding type semiconductor device as set forth in claim 1, wherein said first thin metal wire, said third thin metal wire and said at least one second thin metal wire located intermediate between said first and third thin metal wires are disposed within a width of 700 μ

m.

4. The wire-bonding type semiconductor device as set forth in claim 2, wherein said first thin metal wire, said third thin metal wire and said at least one second thin metal wire located intermediate between said first and third thin metal wires are disposed within a width of 700 μ

m.

5. The wire-bonding type semiconductor device as set forth in claim 2, wherein said wire-bonding type semiconductor device has a plastic ball grid array structure.

6. The wire-bonding type semiconductor device as set forth in claim 2, wherein said semiconductor chip is mounted on a package constituted of a multi-layered substrate.

7. The wire-bonding type semiconductor device as set forth in claim 5, wherein said at least one second thin metal wire located intermediate between said first and third thin metal wires is a wire for emitting a signal therefrom.

8. The wire-bonding type semiconductor device as set forth in claim 6, wherein said at least one second thin metal wire located intermediate between said first and third thin metal wires is a wire for emitting a signal therefrom.

9. A wire-bonding type semiconductor device comprising:

a semiconductor chip;

a plurality sets of electrode pads formed on said semiconductor chip, each set including a power supply electrode, at least one signal electrode pad and a ground electrode pad arranged in this order;

a mount on which said semiconductor chip is placed, said mount being formed with the same number of extensions as the number of said ground electrode pads, said extensions acting as ground leads;

the same number of power supply leads as the number of said ground electrode pads;

the same number of signal leads as the number of said ground electrode pads;

said power supply leads, said signal leads and said extensions acting as ground leads being arranged in this order; and

metal wires for connecting each of said power supply electrode pads, signal electrode pads and ground electrode pads to said power supply leads, said signal leads and said extensions, respectively, said metal wires being disposed substantially in parallel with one another and having substantially the same length.

10. The wire-bonding type semiconductor device as set forth in claim 9, wherein said extensions are short-circuited with one another in said mount so that ground external terminals are smaller in number than said ground electrode pads.

11. The wire-bonding type semiconductor device as set forth in claim 9, wherein said power supply leads are electrically connected to one another by power supply planes through through-holes formed throughout said package, to external terminals disposed on a lower surface of said package.

12. The wire-bonding type semiconductor device as set forth in claim 9, wherein said metal wires are disposed within a width of 700 μ

m.

13. A wire-bonding type semiconductor device comprising:

a multi-layered substrate;

a semiconductor chip mounted on said multi-layered substrate;

a plurality of power supply electrode pads formed on said semiconductor chip;

a plurality of signal electrode pads formed on said semiconductor chip;

a plurality of ground electrode pads formed on said semiconductor chip;

said power supply electrode pads, said signal electrode pads and said ground electrode pads being arranged on said semiconductor chip so that at least one signal electrode pad is always disposed intermediate between a power supply electrode pad and a ground electrode pad,

a plurality of power supply leads formed on a first layer of said multi-layered substrate;

a plurality of signal leads formed on a first layer of said multi-layered substrate;

a plurality of ground leads formed on a first layer of said multi-layered substrate;

a plurality of first thin metal wires for electrically connecting said power supply electrode pads to said power supply leads;

a plurality of second thin metal wires for electrically connecting said signal electrode pads to said signal leads;

a plurality of third thin metal wires for electrically connecting said ground electrode pads to said ground leads;

said first, second and third thin metal wires are designed so that a first thin metal wire, a third thin metal wire and at least one second thin metal wire located intermediate between said first and third thin metal wires are disposed substantially in parallel with one another and have substantially the same length,

the same number of signal planes as the number of said signal electrode pads, said signal planes being formed on said first layer of said multi-layered substrate, said signal leads being connected to external terminals through said signal planes;

a plurality of power supply planes formed on a second layer of said multi-layered substrate, said power supply leads being connected to said power supply planes through through-holes formed throughout said multi-layered substrate, and converged with one another so that said power supply leads are connected to external terminals which are smaller in number than said power supply electrode pads; and

a plurality of ground planes formed on a third layer of said multi-layered substrate, said ground leads being connected to said ground planes through metal plating formed on a sidewall of said multi-layered substrate, and converged with one another so that said ground leads are connected to external terminals which are smaller in number than said ground electrode pads.

14. The wire-bonding type semiconductor device as set forth in claim 13, wherein said first layer of said multi-layered substrate is disposed on or above said second layer, and said second layer is disposed on or above said third layer.

15. The wire-bonding type semiconductor device as set forth in claim 13, wherein said first thin metal wire, said third thin metal wire and said at least one second thin metal wire located intermediate between said first and third thin metal wires are disposed within a width of 700 μ

m.