One pin error amplifier and switched soft-start for an eight pin PFC-PWM combination integrated circuit converter controller

• US 5,798,635 A
• Filed: 02/06/1997
• Issued: 08/25/1998
• Est. Priority Date: 06/20/1996
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Micro Linear Corporation (Qorvo, Inc.)
• Inventors: Yu, Donald, Chee, Alland, Hwang, Jeffrey H., Hsu, Calvin
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US08/796,128
• Time in Patent Office: 565 Days
• Field of Search: 323/222, 323/223, 323/226, 323/273, 323/274, 323/282, 323/284, 323/207, 363/20, 363/21, 363/37, 363/79, 363/89, 363/97, 363/101, 363/124, 363/131
• US Class Current: 323/222
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A combination PFC-PWM integrated circuit converter controller having a power factor correction stage and a pulse-width modulation stage. The power factor correction stage provides unity power factor and a regulated intermediate output voltage by sensing a current in the power factor correction circuit and by sensing the regulated intermediate output voltage in a voltage control loop. The regulated intermediate output voltage is sensed by an error amplifier that includes a current mirror. A dc supply voltage for powering the integrated circuit is generated that is representative of the regulated intermediate output voltage. The dc supply voltage is sensed for an overvoltage protection function. By sensing the intermediate regulated output voltage in the voltage control loop and by sensing the dc supply voltage for overvoltage protection, a component failure is less likely to affect both functions than if a single voltage was sensed for both functions. The pulse-width modulation stage waits a predetermined delay time after start up for the output voltage to rise before beginning the pulse-width modulation function. The delay time is determined by an amount of time taken to charge a capacitor to a predetermined voltage after start up. The capacitor is charged by a current source that is switched on and off according to a clock signal such that the capacitor is charged only a portion of time. Therefore, a larger current source may be used than otherwise which results in more reliable control of the delay time.

Claims

1. A converter controller for controlling a converter, the converter having a power factor correction stage, the power factor correction stage having a control loop for forming a regulated output voltage at an output node wherein the control loop comprises an error amplifier, the error amplifier comprising:

a. a first resistor having a first terminal and a second terminal wherein the first terminal of the first resistor is coupled to the output node of the power factor correction stage and the second terminal of the first resistor forms an output node of the error amplifier; and

b. means for drawing a constant current from the output node of the error amplifier.

2. The converter controller according to claim 1 wherein the power factor correction stage comprises a switch coupled to a control a current in an inductor for charging a capacitor to the regulated output voltage and wherein the control loop further comprises:

a. means for forming a voltage representative of current in the inductor;

b. means for integrating a voltage generated at an output node of the error amplifier for forming an integrated voltage; and

c. means for comparing the integrated voltage to the voltage representative of the current in the inductor, the means for comparing coupled to control the switch.

3. The converter controller according to claim 1 wherein the means for drawing a constant current comprises a current mirror.

4. The converter controller according to claim 1 wherein the means for drawing a constant current comprises:

a. a current source for generating a constant current;

b. a first transistor having a base, a collector and an emitter wherein the collector of the first transistor is coupled to the base of the first transistor and to the current source; and

c. a second transistor having a base, a collector and an emitter wherein the base of the second transistor is coupled to the base of the first transistor and to the collector of the second transistor and the emitter of the second transistor is coupled to the emitter of the first transistor and wherein the collector of the second transistor is coupled to the second terminal of the first resistor.

5. The converter controller according to claim 1 wherein the means for drawing a constant current comprises:

a. a current source for generating a constant current;

b. a first transistor having a gate, a drain and a source wherein the drain of the first transistor is coupled to the gate of the first transistor and to the current source; and

c. a second transistor having a gate, a drain and a source wherein the gate of the second transistor is coupled to the gate of the first transistor and to the drain of the second transistor and the source of the second transistor is coupled to the source of the first transistor and wherein the drain of the second transistor is coupled to the second terminal of the first resistor.

6. The converter controller according to claim 1 wherein the converter further comprises a circuit for forming a supply voltage for the converter controller wherein the circuit for forming the supply voltage is coupled to the power factor correction stage and wherein the converter controller comprises an overvoltage protection circuit coupled to monitor the supply voltage wherein the overvoltage protection circuit and the voltage control loop each prevent the regulated output voltage from becoming excessive.

7. The converter controller according to claim 1 wherein the converter further comprises a pulse-width modulation stage coupled to the output node of the power factor correction stage for receiving the regulated output voltage.

8. The converter controller according to claim 7 wherein the pulse-width modulation stage comprises means for preventing a voltage regulating function of the pulse-width modulation stage from beginning until a after predetermined amount of time has elapsed from start-up of the converter.

9. The converter controller according to claim 8 wherein the converter controller is an integrated circuit having no more than eight pins.

10. The converter controller according to claim 8 wherein the means for preventing comprises a current source for charging a capacitor to a predetermined voltage wherein the current source only charges the capacitor during periodic intervals.

11. The converter controller according to claim 1 further comprising a compensation element coupled to the output of the error amplifier.

12. The converter controller according to claim 11 wherein the compensation element comprises a second resistor and a capacitor coupled in series.

13. A converter controller for controlling a converter, the converter comprising a power factor correction stage wherein the power factor correction stage comprises means for switching coupled to alternately charge a first inductor and to discharge the first inductor into an output capacitor for forming a regulated output voltage across the output capacitor and means for forming a supply voltage for providing power to the converter controller wherein the means for forming the supply voltage comprises a second inductor inductively coupled to the first inductor, and wherein the converter controller comprises:

a. means for controlling the means for switching in a feedback loop for maintaining the regulated output voltage at a desired level, the means for controlling coupled to the output capacitor and to the means for switching; and

b. means for disabling coupled to the means for switching for disabling the means for switching when a level of voltage formed by the means for forming the supply voltage exceeds a predetermined level.

14. The converter controller according to claim 13 wherein the means for controlling the means for switching in a feedback loop comprises:

a. a current source for generating a constant current;

b. a first transistor having a base, a collector and an emitter wherein the collector of the first transistor is coupled to the base of the first transistor and to the current source;

c. a second transistor having a base, a collector and an emitter wherein the base of the second transistor is coupled to the base of the first transistor and to the collector of the second transistor and the emitter of the second transistor is coupled to the emitter of the first transistor; and

d. a resistor having a first terminal and a second terminal wherein the first terminal of the resistor is coupled to receive the regulated output voltage and the second terminal of the resistor is coupled to the collector of the second transistor.

15. The converter controller according to claim 13 wherein the means for controlling the means for switching comprises:

a. a current source for generating a constant current;

b. a first transistor having a gate, a drain and a source wherein the drain of the first transistor is coupled to the gate of the first transistor and to the current source; and

c. a second transistor having a gate, a drain and a source wherein the gate of the second transistor is coupled to the gate of the first transistor and to the drain of the second transistor and the source of the second transistor is coupled to the source of the first transistor; and

d. a resistor having a first terminal and a second terminal wherein the first terminal of the resistor is coupled to receive the regulated output voltage and the second terminal of the resistor is coupled to the drain of the second transistor.

16. A converter controller for controlling a converter, the converter having a pulse-width modulation stage, the pulse width modulation stage comprising:

a. a capacitor;

b. means for charging the capacitor with a first current during periodic intervals upon start-up of the converter;

c. means for charging the capacitor with a second current during alternate intervals; and

d. means for preventing the pulse-width modulation function from beginning until after a voltage across the capacitor has risen to a predetermined level.

17. The converter controller according to claim 16 wherein the second current is substantially zero.

18. The converter controller according to claim 16 further comprising a power factor correction stage wherein the power factor correction stage comprises:

a. means for switching coupled to alternately charge a first inductor and to discharge the first inductor into an output capacitor for forming a regulated output voltage across the output capacitor wherein the pulse-width modulation stage is coupled to the output capacitor for receiving the regulated output voltage;

b. means for controlling the means for switching in a feedback loop for maintaining the regulated output voltage at a desired level, the means for controlling coupled to the output capacitor and to the means for switching;

c. means for forming a supply voltage for providing power to the converter controller wherein the means for forming comprises a second inductor inductively coupled to the first inductor; and

d. means for disabling coupled to the means for switching for disabling the means for switching when a level of voltage formed by the means for forming exceeds a predetermined level.

19. The converter controller according to claim 18 wherein the converter controller is an integrated circuit having no more than eight pins.

20. The converter controller according to claim 18 wherein the means for controlling the means for switching comprises:

a. a current source for generating a constant current;

b. a first transistor having a base, a collector and an emitter wherein the collector of the first transistor is coupled to the base of the first transistor and to the current source;

c. a second transistor having a base, a collector and an emitter wherein the base of the second transistor is coupled to the base of the first transistor and to the collector of the second transistor and the emitter of the second transistor is coupled to the emitter of the first transistor; and

d. a resistor having a first terminal and a second terminal wherein the first terminal of the resistor is coupled to receive the regulated output voltage and the second terminal of the resistor is coupled to the collector of the second transistor.

21. The converter controller according to claim 18 wherein the means for controlling the means for switching means comprises:

a. a current source for generating a constant current;

b. a first transistor having a gate, a drain and a source wherein the drain of the first transistor is coupled to the gate of the first transistor and to the current source; and

c. a second transistor having a gate, a drain and a source wherein the gate of the second transistor is coupled to the gate of the first transistor and to the drain of the second transistor and the source of the second transistor is coupled to the source of the first transistor;

d. a resistor having a first terminal and a second terminal wherein the first terminal of the resistor is coupled to receive the regulated output voltage and the second terminal of the resistor is coupled to the drain of the second transistor.

22. An error amplifier having an input node and output node, wherein a change in an input voltage level applied to the input node results in a change in an output voltage formed at the output node wherein the change in the output voltage relative to an expected quiescent value for the output voltage is greater than the change in the input voltage relative to an expect quiescent value for the input voltage, the error amplifier comprising:

a. a first resistor having a first terminal and a second terminal wherein the first terminal of the first resistor forms the input node for the error amplifier and the second terminal of the first resistor forms the output node for the error amplifier; and

b. means for drawing a constant current through the resistor.

23. The error amplifier according to claim 22 wherein the means for drawing a constant current comprises a current mirror.

24. The error amplifier according to claim 22 wherein the means for drawing a constant current comprises:

a. a current source for generating a constant current;

b. a first transistor having a base, a collector and an emitter wherein the collector of the first transistor is coupled to the base of the first transistor and to the current source; and

c. a second transistor having a base, a collector and an emitter wherein the base of the second transistor is coupled to the base of the first transistor and to the collector of the second transistor and the emitter of the second transistor is coupled to the emitter of the first transistor and wherein the collector of the second transistor is coupled to the second terminal of the first resistor.

25. The amplifier according to claim 22 wherein the means for drawing a constant current comprises:

a. a current source for generating a constant current;

b. a first transistor having a gate, a drain and a source wherein the drain of the first transistor is coupled to the gate of the first transistor and to the current source; and

c. a second transistor having a gate, a drain and a source wherein the gate of the second transistor is coupled to the gate of the first transistor and to the drain of the second transistor and the source of the second transistor is coupled to the source of the first transistor and wherein the drain of the second transistor is coupled to the second terminal of the first resistor.

26. The amplifier according to claim 22 further comprising a compensation element coupled to the output of the error amplifier.

27. The amplifier according to claim 26 wherein the compensation element comprises a second resistor and a capacitor coupled in series.