FRAM, FRAM card, and card system using the same

• US 5,798,964 A
• Filed: 08/23/1995
• Issued: 08/25/1998
• Est. Priority Date: 08/29/1994
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Toshiba Corporation
• Inventors: Shimizu, Mitsuru, Tanaka, Sumio
• Primary Examiner(s): YOO, DO H
• Application Number:
  US08/518,440
• Time in Patent Office: 1,098 Days
• Field of Search: 365/145, 365/149, 365/65, 365/226
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential. The switching transistors are controlled by the power on reset signal so that they are on for a predetermined period of time.

Claims

1. A ferroelectric memory comprising:

a memory cell array having memory cells arranged in the form of a matrix having rows and columns, each memory cell including an information storage capacitor utilizing a ferroelectric material as an inter-plate insulation film and a MOS transistor for transferring electrical charges, the information storage capacitor and the MOS transistor being connected in series;

a plurality of word lines, each of the word lines being connected in common to gates of the MOS transistors of the memory cells belonging to one of the rows;

a plurality of plate lines, each of the plate lines being connected in common to plates of the information storage capacitors of the memory cells belonging to one of the rows;

a plurality of bit lines, each of the bit lines being connected in common to one end of the MOS transistors of the memory cells belonging to one of the columns;

a word line selection circuit for selecting at least one of said plurality of word lines according to an address signal;

a plate line selection circuit for selecting at least one of said plurality of plate lines according to said address signal the plate line selection circuit controlling the voltage of selected plate lines;

a power on reset circuit for generating a power on reset signal of a predetermined level, the power on reset signal being generated for a predetermined period of time in response to a power supply being turned on; and

an erroneous programming prevention circuit including a plurality of first switching transistors, each of the first switching transistors being connected between one of said bit lines and one or more first nodes at a first predetermined potential,

wherein said plurality of first switching transistors are controlled by said power on reset signal so that the first switching transistors are on for the predetermined period of time after the power supply is turned on so as to supply the first predetermined potential to the bit lines during the predetermined period of time.

2. The ferroelectric memory according to claim 1, wherein said erroneous programming prevention circuit also includes a plurality of second switching transistors, each of the second switching transistors being connected between one of said plate lines and one or more second nodes at a second predetermined potential, and

said plurality of second switching transistors are controlled by said power on reset signal so that the second switching transistors are on for the predetermined period of time after the power supply is turned on.

3. The ferroelectric memory according to claim 2, wherein said power on reset circuit generates the power on reset signal at a "High" level for said predetermined period of time after the power supply is turned on,

said first and second switching transistors are NMOS transistors, and

a ground potential is supplied to said first and second nodes as said first and second predetermined potentials.

4. A ferroelectric memory comprising:

a memory cell array having memory cells arranged in a matrix having rows and columns, each memory cell including an information storage capacitor utilizing a ferroelectric material as an inter-plate insulation film and a MOS transistor for transferring electrical charges, each MOS transistor of the memory cells of one of the rows being commonly connected by a word line, one electrode of each information storage capacitor of the memory cells of one of the rows being commonly connected by a plate line, and one terminal of each MOS transistor of the memory cells of one of the columns being commonly connected by a bit line;

a power on circuit for outputting a first signal of a predetermined period in response to a power supply being turned on; and

means for setting each plate line and each bit line to a first potential in response to said first signal.

5. The ferroelectric memory according to claim 4, wherein said means for setting is used in combination with a means for driving said plate lines.

6. The ferroelectric memory according to claim 4, wherein said means for setting is used in combination with a means for equalizing said bit lines.

7. The ferroelectric memory according to claim 4, wherein said means for setting is used in combination with sense amplifier circuits, which are connected to the bit lines.

8. The ferroelectric memory according to claim 4, wherein the first potential is a ground potential and the means for setting sets each plate line and each bit line to the ground potential when the first signal is active.

9. A ferroelectric memory comprising:

a memory cell array having memory cells arranged in a matrix having rows and columns, each memory cell having an information storage capacitor utilizing a ferroelectric material as an inter-plate insulation film and a MOS transistor for transferring electrical charges, each MOS transistor of the memory cells of one of the rows being commonly connected by a word line, one electrode of each information storage capacitor of the memory cells of one of the rows being commonly connected by a plate electrode line, and one terminal of each MOS transistor of the memory cells of one of the columns being commonly connected by a bit line;

a power on circuit for outputting a first signal of a predetermined period in response to a power supply be turned on; and

means for setting each plate electrode line and each word line to a first potential in response to said first signal.

10. The ferroelectric memory according to claim 9, wherein said means for setting is used in combination with a means for driving said word lines.

11. The ferroelectric memory according to claim 9, wherein said means for setting is used in combination with a means for equalizing the bit lines.

12. The ferroelectric memory according to claim 9, wherein said means for setting is used in combination with sense amplifier circuits, which are connected to the lines.

13. The ferroelectric memory according to claim 9, wherein the first potential is a ground potential and the means for setting sets each plate electrode line and each word line to the ground potential when the first signal is active.