FET having gate insulating film of nonuniform thickness and asymmetrical source and drain structures

• US 5,801,416 A
• Filed: 01/24/1996
• Issued: 09/01/1998
• Est. Priority Date: 03/13/1995
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Keon-soo, Choi, Yong-bae
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US08/590,748
• Time in Patent Office: 951 Days
• Field of Search: 257/491, 257/412, 257/413, 257/655, 257/409, 257/408, 257/335, 257/336, 257/344, 257/404, 257/285, 257/496
• US Class Current: 257/335
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A high withstand voltage transistor and a method for manufacturing the same are disclosed. The transistor includes a semiconductor substrate, a field oxide film, a channel region formed of first and second channel regions each having a different concentration level, a gate insulating film having a step difference, a gate electrode having a step difference, a drain region including first, second, and third impurity regions, a source region including first and third impurity regions, a spacer, an interlayer dielectric film and a metal electrode. Threshold voltage can be maintained to an appropriate level, junction break voltage can be increased, and the punchthrough characteristic can also be enhanced.

Claims

1. A high withstand voltage transistor comprising:

a semiconductor substrate;

a channel stop region located on said substrate and formed of the same impurity as that of said substrate;

field oxide films formed on said channel stop region;

a channel region having a nonuniform impurity concentration on an active region between said field oxide films;

a gate insulating film having a step difference formed on said channel region;

a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n⁺ and n^- type impurities, respectively;

a gate electrode having a step difference formed on said gate insulating film;

a spacer formed on the sidewalls of said gate electrode;

an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and

a metal electrode formed by filling said contact hole;

wherein said channel region comprises a first channel region at low concentration and a second channel region at high concentration formed by ion-implanted impurities of the same conductivity type as that of the semiconductor substrate; and

wherein a first gate insulating film region is formed on said first channel region, and a second gate insulating film region is formed on said second channel region.

2. A high withstand voltage transistor according to claim 1, wherein said first gate insulating film region comprises a thick insulating film and said second gate insulating film region comprises a thin insulating film.

3. A high withstand voltage transistor according to claim 1, wherein said first channel region is adjacent to said drain region, and said second region is formed adjacent to said source region.

4. A high withstand voltage transistor comprising:

a semiconductor substrate;

a channel stop region located on said substrate and formed of the same impurity as that of said substrate;

field oxide films formed on said channel stop region;

a channel region having a nonuniform impurity concentration on an active region between said field oxide films;

a gate insulating film having a step difference formed on said channel region;

a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n⁺ and n^- type impurities, respectively;

a gate electrode having a step difference formed on said gate insulating film;

a spacer formed on the sidewalls of said gate electrode;

an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and

a metal electrode formed by filling said contact hole;

wherein said gate insulating film comprises a thick first gate insulating film region and a thin second gate insulating film region; and

wherein said first gate insulating film region is formed on a first channel region, and said second gate insulating film region is formed on a second channel region.

5. A high withstand voltage transistor according to claim 4, wherein said first channel region comprises a low concentration of impurities and said second channel region includes a high concentration of impurities, said impurities being the same conductivity type as that of said semiconductor substrate.

6. A high withstand voltage transistor according to claim 4, wherein said first channel region is adjacent to said drain region, and said second region is formed adjacent to said source region.

7. A high withstand voltage transistor comprising:

a semiconductor substrate;

a channel stop region located on said substrate and formed of the same impurity as that of said substrate;

field oxide films formed on said channel stop region;

a channel region having a nonuniform impurity concentration on an active region between said field oxide films;

a gate insulating film having a step difference formed on said channel region;

a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n⁺ and n^- type impurities, respectively;

a gate electrode having a step difference formed on said gate insulating film;

a spacer formed on the sidewalls of said gate electrode;

an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and

a metal electrode formed by filling said contact hole;

wherein said drain region includes shallow first and deep second impurity regions at low concentration formed of an opposite conductive impurity to that of said semiconductor substrate and a shallow third impurity region at high concentration.

8. A high withstand voltage transistor according to claim 7, wherein said second impurity region is arranged below said third impurity region.

9. A high withstand voltage transistor according to claim 7, wherein said third impurity region is formed spaced from said gate electrode by a predetermined distance so that said third impurity region does not overlap with said gate electrode.

10. A high withstand voltage transistor comprising:

a semiconductor substrate;

a channel stop region located on said substrate and formed of the same impurity as that of said substrate;

field oxide films formed on said channel stop region;

a channel region having a nonuniform impurity concentration on an active region between said field oxide films;

a gate insulating film having a step difference formed on said channel region;

a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n⁺ and n^- type impurities, respectively;

a gate electrode having a step difference formed on said gate insulating film;

a spacer formed on the sidewalls of said gate electrode;

an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and

a metal electrode formed by filling said contact hole;

wherein said source region includes a shallow first impurity region at low concentration and a shallow third impurity region at high concentration.

11. A high withstand voltage transistor according to claim 10, wherein said third impurity region is formed spaced from said gate electrode by a predetermined distance so that said third impurity region does not overlap with said gate electrode.