Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed

• US 5,802,290 A
• Filed: 12/12/1996
• Issued: 09/01/1998
• Est. Priority Date: 07/29/1992
• Status: Expired due to Term

• Current Assignee: Tarofiss Data Limited Liability Company
• Original Assignee: Virtual Computer Incorporated (Cloud Software Group)
• Inventors: Casselman, Steven M.
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US08/764,029
• Time in Patent Office: 628 Days
• Field of Search: 395/200.31, 395/200.32, 395/200.33, 395/406, 395/500, 395/376
• US Class Current: 709/201
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

A virtual network consists of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each distributed virtual computer has at least two ports connected over respective links to other respective distributed virtual computers on the network. Each distributed virtual computer is connected to or resident within its own host, each host typically being a conventional computer such as a personal computer or a work station, for example, although at least one of the hosts may itself be another virtual computer. Each distributed virtual computer has reconfigurable logic elements such as an FPGA or an array of FPGAs.

Claims

1. A virtual network comprising:

plural distributed virtual computers interconnected over a communication network of individual links;

each distributed virtual computer comprising at least two respective ports each being connected over a respective link to another respective distributed virtual computer in the network;

each distributed virtual computer being connected to or resident within its own host computer;

each distributed virtual computer comprising reconfigurable FPGA logic elements, at least one of the FPGA elements being configured to have control capability over at least some of the remaining FPGA elements to react to instructions received from a host or from other nodes on the network to re-configure FPGA elements in the computation array to carry out a required task; and

wherein at least the one or FPGA element is configured to have compiling capability to generate configuration bit files from received instructions defining how said at least some of said remaining FPGA elements are to be reconfigured so as to enable them to carry out said received instructions.

2. The virtual network of claim 1 wherein said one FPGA element configured to have control capability comprises plural FPGAs and said remaining FPGA elements comprises other plural FPGAs.

3. The virtual network of claim 1 wherein said one FPGA element configured to have control capability comprises FPGA elements on a single FPGA and said remaining FPGA elements comprise FPGA elements on another single FPGA.

4. The virtual computer of claim 1 wherein said one FPGA element configured to have control capability constitutes a portion of FPGA elements in a single FPGA.

5. The virtual computer of claim 1 wherein at least some of said remaining FPGA elements have a logic configuration suitable for executing tasks supporting a network protocol.

6. The virtual computer of claim 5 wherein at least some of said remaining FPGA elements have a logic configuration suitable for performing packet header translation.

7. A virtual network comprising:

plural distributed virtual computers, each of said plural distributed virtual computers being adapted for connection with a respective host;

plural communication links connecting each of said plural distributed virtual computers with at least two others of said plural distributed virtual computers;

each distributed virtual computer comprising;

(A) at least two respective ports each being connected to a respective one of said links;

(B) plural reconfigurable FPGA logic elements comprising;

(1) a control set of reconfigurable FPGA elements being configured to have control capability for compiling a request received from a host or from other nodes on the network to generate configuration bit files defining a logic configuration for carrying out a process corresponding to said request;

(2) a computation set of reconfigurable FPGA elements adapted to be reconfigured by said control set of FPGA elements in accordance with said configuration bit files so as to be capable of carrying out a corresponding process on operand data; and

wherein at least the control set of FPGA elements are configured to have compiling capability to generate configuration bit files from received instructions defining how said computation set of FPGA elements are to be reconfigured so as to enable them to carry out processes corresponding to said received instructions.

8. The virtual network of claim 7 wherein said request comprises one of:

(a) an instruction of a program, (b) a set of instructions, (c) a program, (d) an algorithm.

9. The virtual network of claim 7 wherein said control set of FPGA elements comprises plural FPGAs and said computation set of FPGA elements comprises other plural FPGAs.

10. The virtual network of claim 7 wherein said control set of FPGA elements comprises a first FPGA having plural FPGA elements and said computation set of FPGA elements comprise a second FPGA having plural FPGA elements.

11. The virtual computer of claim 7 wherein said control set of FPGA elements constitutes a portion of FPGA elements in a single FPGA.

12. The virtual computer of claim 7 wherein at least some of said FPGA elements have a logic configuration suitable for executing tasks supporting a network protocol.

13. The virtual computer of claim 7 wherein at least some of said FPGA elements have a logic configuration suitable for performing packet header translation.

14. A method of operating as a computer a reconfigurable node in a computer network of plural reconfigurable nodes interconnected by plural communication links, said reconfigurable node comprising reconfigurable logic array elements which are reconfigurable in accordance with a configuration bit file so as to become adapted to perform an operation in accordance with a predetermined reconfiguration algorithm which generates said configuration bit file from a definition of said operation, said method comprising:

storing an executable code defining a sequence of operations to be executed in sequence;

executing said executable code operation-by-operation in order of said sequence, said executing comprising;

at the time of the execution of at least one of said operations, computing exclusively from the portion of said executable code defining said one operation a corresponding configuration bit file representative of said one operation in accordance with said reconfiguration algorithm, and

reconfiguring said reconfigurable node in accordance with said corresponding configuration bit file.

15. The method of claim 14 wherein said computing comprises performing at least a part of said reconfiguration algorithm on said portion of said executable code defining said one operation to obtain said corresponding configuration bit file.

16. The method of claim 15 wherein said part of said reconfiguration algorithm comprises at least a downloading function of said reconfiguration algorithm.

17. The method of claim 14 wherein said computing step is capable of producing any configuration bit file required to represent said one operation within the complete set of all configuration bit files of which said reconfiguration algorithm is capable of producing.

18. A method of operating a reconfigurable logic array which is reconfigurable in response to different configuration bit files defining different logic configurations adapted to perform different operations, said configuration bit files susceptible of being produced by a reconfiguration algorithm based upon definitions of said different operations, said method comprising:

storing an executable code defining a sequence of operations to be executed in sequence;

executing said executable code operation-by-operation in order of said sequence, said executing comprising;

at the time in said sequence for execution of at least one of said operations, computing exclusively from the portion of said executable code defining said one operation a corresponding configuration bit file representative of said one operation in accordance with said reconfiguration algorithm, and

reconfiguring said reconfigurable logic array in accordance with said corresponding configuration bit file in time for said reconfigurable logic array to carry out said one operation in the order of said sequence.

19. The method of claim 18 wherein said computing comprises performing at least a part of said reconfiguration algorithm on said portion of said executable code defining said one operation to obtain said corresponding configuration bit file.

20. The method of claim 19 wherein said part of said reconfiguration algorithm comprises at least a downloading function of said reconfiguration algorithm.

21. The method of claim 18 wherein said computing step produces whatever configuration bit file is sufficient for said one operation within the complete set of all configuration bit files of which said reconfiguration algorithm is capable of producing.

22. The method of claim 18 wherein said computing comprises performing the entirety of said reconfiguration algorithm on said portion of said executable code defining said one operation to obtain said corresponding configuration bit file.

23. A method of operating a reconfigurable logic array reconfigurable in response to respective configuration bit files defining respective logic configurations into which said reconfigurable logic array can be configured, at least one of said respective logic configurations at a time, to perform respective operations, said respective configuration bit files susceptible of being produced by a reconfiguration algorithm based upon definitions of said respective operations, said method comprising:

storing an executable code comprising images of operations in a sequence of operations to be executed;

executing said executable code operation-by-operation in order of said sequence, said executing comprising;

at the time in said sequence for execution of at least one of said operations, computing exclusively from said image of the one operation a corresponding configuration bit file representative of said one operation in accordance with said reconfiguration algorithm, and

reconfiguring said reconfigurable logic array in accordance with said corresponding configuration bit file in time for said reconfigurable logic array to carry out said one operation in the order of said sequence.

24. The method of claim 23 wherein said image of said operation is a self-contained complete description of said one operation.

25. The method of claim 23 wherein said computing comprises performing at least a part of said reconfiguration algorithm on said image of said one operation to obtain said corresponding configuration bit file.

26. The method of claim 25 wherein said part of said reconfiguration algorithm comprises at least a downloading function of said reconfiguration algorithm.

27. The method of claim 26 wherein said computing comprises performing the entirety of said reconfiguration algorithm on said portion of said executable code defining said one operation to obtain said corresponding configuration bit file.

28. The method of claim 23 wherein said computing step produces whatever configuration bit file is sufficient to represent said one operation within the complete set of all configuration bit files of which said reconfiguration algorithm is capable of producing.