Memory in a programmable logic device

  • US 5,804,986 A
  • Filed: 12/29/1995
  • Issued: 09/08/1998
  • Est. Priority Date: 12/29/1995
  • Status: Expired due to Term
First Claim
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1. A programmable logic device comprising:

  • an input;

    an interconnect matrix coupled to said input; and

    a plurality of logic blocks coupled to said interconnect matrix, wherein one of said plurality of logic blocks comprises;

    a first programmable logic element coupled to the interconnect matrix, said first programmable logic element receiving a first plurality of control signals and a plurality of address signals from said interconnect matrix, and outputting a second plurality of control signals; and

    a multi-port storage element having a plurality of ports, wherein said multi-port storage element is coupled to the interconnect matrix and the first programmable logic element, said multi-port storage element receiving said second plurality of control signals from said first programmable logic element and receiving a plurality of data input signals and the plurality of address signals from said interconnect matrix, said multi-port storage element outputting a first plurality of data signals.

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