Synchronous semiconductor memory having a burst transfer mode with a plurality of subarrays accessible in parallel via an input buffer

  • US 5,805,504 A
  • Filed: 11/29/1996
  • Issued: 09/08/1998
  • Est. Priority Date: 11/29/1995
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory having a burst mode transfer function, comprising:

  • a plurality of memory cell sub-arrays which are accessible in parallel and simultaneously;

    a plurality of internal data buses for inputting and outputting data to and from said plurality of memory cell sub-arrays, in parallel; and

    an input buffer circuit receiving an external data signals continuously and sequentially in time in synchronism with a reference clock signal, for converting said receiving serial data into a parallel data under control of an external command signal and an external address signal, so as to distribute said parallel data to said plurality of internal data buses,the input buffer circuit including a shift register circuit composed of a plurality of cascade-connected registers and for latching and shifting said external data signals only in response to said reference clock signal, said cascade-connected registers outputting, in parallel, said data latched in said respective registers, and a register output selecting means receiving said data signals outputted in parallel from said cascade-connected registers, for distributing said received parallel data signals, in parallel, to said plurality of internal data buses in accordance with said external address signal.

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