Substrate biasing circuit having controllable ring oscillator
First Claim
1. A substrate biasing circuit comprising a charge pump circuit receiving a drive pulse signal and generating a substrate-bias voltage at an output terminal in response thereto, said charge pump circuit including an output transistor coupled to said output terminal to output said substrate-bias voltage, a ring oscillator including a plurality of delayed-inverter circuits connected in a ring form to produce said drive pulse signal, said drive pulse signal having a frequency, and a current control circuit controlling each of said delayed-inverter circuits such that the frequency of said drive pulse signal is increased when a threshold voltage of said output transistor is larger than a predetermined value and is decreased when said threshold voltage of said output transistor is smaller than said predetermined value.
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Accused Products
Abstract
A substrate biasing circuit is disclosed which includes a ring oscillator oscillating to a drive pulse signal, a charge pump circuit connected to the ring oscillator to receive the drive pulse signal and generating a substrate-bias voltage in response thereto, and a current control circuit connected to the ring oscillator. The ring oscillator includes a plurality of delay circuits and the current control circuit controls each of the delay circuits such that a current flowing there through is stabilized against the variation in power voltage and relative to a threshold voltage of a transistor for the charge pump circuit.
84 Citations
9 Claims
- 1. A substrate biasing circuit comprising a charge pump circuit receiving a drive pulse signal and generating a substrate-bias voltage at an output terminal in response thereto, said charge pump circuit including an output transistor coupled to said output terminal to output said substrate-bias voltage, a ring oscillator including a plurality of delayed-inverter circuits connected in a ring form to produce said drive pulse signal, said drive pulse signal having a frequency, and a current control circuit controlling each of said delayed-inverter circuits such that the frequency of said drive pulse signal is increased when a threshold voltage of said output transistor is larger than a predetermined value and is decreased when said threshold voltage of said output transistor is smaller than said predetermined value.
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7. A circuit comprising:
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a first transistor of a first channel type having a source connected to a first voltage supply line, a drain connected to a first node and a gate connected to said first node; a second transistor of said first channel type having a source connected to said first node, a drain connected to a second node and a gate connected to said second node; a resistive element connected between said second node and a second power supply line; and a third transistor of said first channel type having a source connected to said first power supply line, a drain connected to an output node and a gate connected to said second node, such that a current at said output node is determined by a threshold voltage of at least one of said first, second and third transistors.
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8. A circuit comprising:
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a delayed-invertor including, a first transistor of a first channel type connected between a first power supply line and a first node and having a gate connected to a first control terminal; a second transistor of said first channel type connected between said first node and an output node and having a gate connected to an input node; a third transistor of a second channel type connected between said output node and a second node and having a gate connected to said input node, said first channel type being opposite to said second channel type, and a fourth transistor of said second channel type connected between said second node and a second power supply line and having a gate connected to a second control terminal; and a current control circuit including, a fifth transistor of said first channel type connected between said first power supply line and a third node and having a gate connected to said third node; a sixth transistor of said first channel type connected between said third node and a fourth node and having a gate connected to said fourth node; a resistive element connected between said fourth node and said second power supply line; a seventh transistor of said first channel type connected between said first power supply line and said second control terminal and having a gate connected to said fourth node; an eighth transistor of said second channel type connected between said second control terminal and said second power supply line and having a gate connected to said second control terminal; a ninth transistor of said first channel type connected between said first power supply line and said first control terminal and having a gate connected to said first control terminal; and a tenth transistor of said second channel type connected between said first control terminal and said second power supply line and a gate connected to said second control terminal.
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9. A substrate biasing circuit comprising:
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a charge pump circuit receiving a drive pulse signal at an input terminal and generating a substrate bias voltage at an output terminal, said charge pump circuit comprising, an inverter with an inverter input connected to said input terminal and to an input to a first capacitor, and with an inverter output connected to inputs to second and third capacitors, a first transistor with one terminal connected to said output terminal, a second terminal and a gate connected to an output from said second capacitor, and a back gate connected to said inverter output, a second transistor with one terminal connected to said second capacitor output, a second terminal connected to ground, a gate connected to an output from said first capacitor, and a back gate connected to said inverter output, a third transistor with one terminal connected to said first capacitor output, a second terminal connected to ground, a gate connected to an output from said third capacitor, and a back gate connected to said inverter input, and a fourth transistor with one terminal connected to said third capacitor output, a second terminal and a gate connected to ground, and a back gate connected to said inverter input; a ring oscillator including a plurality of ring-connected delayed-inverter circuits providing said drive pulse signal with a frequency to said input terminal; and a current control circuit controlling said delayed-inverter circuits so that the frequency of the drive pulse signal increases when a threshold voltage of said first transistor is larger than a predetermined value and decreases when the threshold voltage of said first transistor is smaller than the predetermined value.
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Specification