Semiconductor memory

• US 5,808,951 A
• Filed: 09/17/1997
• Issued: 09/15/1998
• Est. Priority Date: 05/13/1981
• Status: Expired due to Fees

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawamoto, Hiroshi, Shimohigashi, Katsuhiro, Masuda, Hiroo, Ikuzaki, Kunihiko
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/951,206
• Time in Patent Office: 363 Days
• Field of Search: 365/182, 365/201, 365/205
• US Class Current: 365/205
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory comprising:

a pair of data lines which are formed substantially in parallel to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of dynamic memory cells, each of which is coupled to one of said word lines and to one of said pair of data lines;

an amplifier a pair of N-channel MOS transistors, a pair of P-channel MOS transistors, a first switching MOS transistor of N-channel type and a second switching MOS transistor of P-channel type, wherein each transistor of said pair of N-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of N-channel MOS transistors, wherein a drain of one of said pair of N-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of N-channel MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of P-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of P-channel MOS transistors, wherein a drain of one of said pair of P-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of P-channel MOS transistors is coupled to the other of said pair of data lines, wherein said first switching MOS transistor has a drain coupled to a source of each of said pair of N-channel MOS transistors and a source coupled to a first potential terminal being supplied with a low-level potential, wherein said second switching MOS transistor has a drain coupled to a source of each of said pair of P-channel MOS transistors and a source coupled to a second potential terminal being supplied with a high-level potential, and wherein said amplifier provides said data lines with said high-level potential and said low-level potential, respectively; and

a precharging circuit including a third switching MOS transistor, a fourth switching MOS transistor and a fifth switching MOS transistor, wherein said third switching MOS transistor has a source-drain path provided between said pair of data lines, wherein said fourth switching MOS transistor has a source-drain path provided between one of said pair of data lines and a third potential terminal being supplied with an intermediate level potential between said high-level potential and said low-level potential, wherein said fifth switching MOS transistor has a source-drain path provided between the other of said pair of data lines and said third potential terminal, and wherein said third, fourth and fifth switching MOS transistors set said pair of data lines at said intermediate level when said plurality of memory cells are in a non-selected state.

2. A semiconductor memory according to claim 1,

wherein said third, fourth and fifth switching MOS transistors are N-channel MOS transistors and have gates supplied with a common control signal.

3. A semiconductor memory comprising:

a pair of data lines which are formed substantially in parallel to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of dynamic memory cells, each of which is coupled to one of said word lines and to one of said pair of data lines;

an amplifier including a pair of N-channel MOS transistors, a pair of P-channel MOS transistors, a first switching MOS transistor of N-channel type and a second switching MOS transistor of P-channel type, wherein each transistor of said pair of N-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of N-channel MOS transistors, wherein a drain of one of said pair of N-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of N-channel MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of P-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of P-channel MOS transistors, wherein a drain of one of said pair of P-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of P-channel MOS transistors is coupled to the other of said pair of data lines, wherein said first switching MOS transistor has a drain coupled to a source of each of said pair of N-channel MOS transistors and a source coupled to a first potential terminal being supplied with a low-level potential, wherein said second switching MOS transistor has a drain supplied to a source of each of said pair of P-channel MOS transistors and a source coupled to a second potential terminal being supplied with a high-level potential, wherein said amplifier provides said data lines with said high-level potential and said low-level potential, respectively, and wherein said first switching MOS transistor and said second switching MOS transistor are turned "on" at the same time; and

a precharging circuit including a third switching MOS transistor, a fourth switching MOS transistor and a fifth switching MOS transistor, wherein said third switching MOS transistor has a source-drain path provided between said pair of data lines, wherein said fourth switching MOS transistor has a source-drain path provided between one of said pair of data lines and a third potential terminal being supplied with an intermediate level potential between said high-level potential and said low-level potential, wherein said fifth switching MOS transistor has a source-drain path provided between the other of said pair of data lines and said third potential terminal, and wherein said third, fourth and fifth switching MOS transistors set said pair of data lines at said intermediate level when said plurality of memory cells are in a non-selected state.

4. A semiconductor memory according to claim 3,

wherein said third, fourth and fifth switching MOS transistors are N-channel MOS transistors and have gates supplied with a common control signal.

5. A semiconductor memory according to claim 3, further comprising:

a sixth switching MOS transistor of N-channel type having a drain coupled to said source of each of said pair of N-channel MOS transistors and a source coupled to said first potential terminal, wherein said sixth switching MOS transistor is turned "on" at a time different from a time when said first switching MOS transistor is turned "on".

6. A semiconductor memory comprising:

a pair of data lines which are formed substantially in parallel to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of dynamic memory cells, each of which is coupled to one of said word lines and to one of said pair of data lines;

an amplifier including a pair of N-channel MOS transistors, a pair of P-channel MOS transistors, a first switching MOS transistor of N-channel type and a second switching MOS transistor of P-channel type, wherein each transistor of said pair of N-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of N-channel MOS transistors, wherein a drain of one of said pair of N-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of N-channel MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of P-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of P-channel MOS transistors, wherein a drain of one of said pair of P-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of P-channel MOS transistors is coupled to the other of said pair of data lines, wherein said first switching MOS transistor has a drain coupled to a source of each of said pair of N-channel MOS transistors and a source coupled to a first potential terminal being supplied with a low-level potential, wherein said second switching MOS transistor has a drain coupled to a source of each of said pair of P-channel MOS transistors and a source coupled to a second potential terminal being supplied with a high-level potential, and wherein said amplifier provides said data lines with said high-level potential and said low-level potential, respectively, and wherein said first switching MOS transistor is turned "on" at a time different from a time when said second switching MOS transistor is turned "on"; and

a precharging circuit including a third switching MOS transistor, a fourth switching MOS transistor and a fifth switching MOS transistor, wherein said third switching MOS transistor has a source-drain path provided between said pair of data lines, wherein said fourth switching MOS transistor has a source-drain path provided between one of said pair of data lines and a third potential terminal being supplied with an intermediate level potential between said high-level potential and said low-level potential, wherein said fifth switching MOS transistor has a source-drain path provided between the other of said pair of data lines and said third potential terminal, and wherein said third, fourth and fifth switching MOS transistors set said pair of data lines at said intermediate level when said plurality of memory cells are in a non-selected state.

7. A semiconductor memory according to claim 6,

wherein said third, fourth and fifth switching MOS transistors are N-channel MOS transistors and have gates supplied with a common control signal.

8. A semiconductor memory according to claim 6, further comprising:

a sixth switching MOS transistor of N-channel type having a drain coupled to said source of each of said pair of N-channel MOS transistors and a source coupled to said first potential terminal, wherein said sixth switching MOS transistor is turned "on" at a time different from a time when said first switching MOS transistor is turned "on".