Driver circuit for addressing core memory and a method for the same

CAFC
  • US 5,812,461 A
  • Filed: 10/29/1996
  • Issued: 09/22/1998
  • Est. Priority Date: 06/14/1990
  • Status: Expired due to Term
First Claim
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1. An improvement in a method for decoding a plurality of virtual ground lines and bit lines in a memory core comprising the steps of:

  • driving all virtual ground lines in said memory core low;

    multiplexing two virtual ground lines in a memory core, by holding a selected first virtual ground line low and keeping a selected second virtual ground line low for memory core discharge; and

    by driving said selected second virtual ground line high for core evaluation;

    evaluating said memory core;

    keeping all unselected virtual ground lines floating during said step of evaluating said memory core; and

    switching said second virtual ground line low for memory core discharge in preparation for subsequent memory core evaluation.

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