Driver circuit for addressing core memory and a method for the same

• US 5,812,461 A
• Filed: 10/29/1996
• Issued: 09/22/1998
• Est. Priority Date: 06/14/1990
• Status: Expired due to Term

• Current Assignee: Creative Integrated Systems Incorporated
• Original Assignee: Creative Integrated Systems Incorporated
• Inventors: Amneus, Robert D., Komarek, James A., Padgett, Clarence W., Tanner, Scott B.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/741,207
• Time in Patent Office: 693 Days
• Field of Search: 365/189.02, 365/189.05, 326/58, 326/82, 326/83, 327/108, 327/109, 327/111, 368/185.16
• US Class Current: 365/189.05
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/126 Virtual ground arrays
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase. Next, during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage. If the selected memory core FET is programmed with a high threshold voltage, the bit line remains floating at the ground level, or it may be held at ground by means of the second virtual ground line, which is held at ground, and by low threshold core FETs, adjacent to the selected core FET, which are connected to the selected word line. The total diffusion capacitance on a virtual ground line is minimized when the memory cells connected to the line are programmed with more logic zeros than logic ones.

Claims

1. An improvement in a method for decoding a plurality of virtual ground lines and bit lines in a memory core comprising the steps of:

driving all virtual ground lines in said memory core low;

multiplexing two virtual ground lines in a memory core, by holding a selected first virtual ground line low and keeping a selected second virtual ground line low for memory core discharge; and

by driving said selected second virtual ground line high for core evaluation;

evaluating said memory core;

keeping all unselected virtual ground lines floating during said step of evaluating said memory core; and

switching said second virtual ground line low for memory core discharge in preparation for subsequent memory core evaluation.

2. The improvement of claim 1 further comprising the step of precharging a BIT line to ground prior to said step of evaluating said core, said BIT line being selectively coupled to said bit lines in said memory.

3. A decoder for producing two memory multiplexing signals, SELV0 and SELV1, capable of driving a large capacitive memory load, said decoder coupled between a high voltage supply and around and comprising:

decode means for selectively decoding an address signal to drive one of said two memory multiplexing signals, SELV0 and SELV1, high and the other low; and

drive means coupled to said decode means and for generating said two memory multiplexing signals, SELV0 and SELV1, in response to said decode means, said drive means being tristated, without generating any current between said high voltage supply and ground when switching between said low and high logic levels of SELV0 and SELV1, whereby noise to ground is reduced.

4. The decoder of claim 3 wherein said drive means is comprised of a pair of two large FETs coupled in series, said memory multiplexing signals, SELV0 and SELV1, being derived respectively from said coupling between one of said pair of said two large FETs, said drive means comprising means for turning each one of said two large FETs off before turning on the other one of said two large FETs in each of said pairs of FETs, so that one of said FETs of each pair will always be off when the other one of said pair of FETs is on.

5. The decoder of claim 3 wherein said memory multiplexing signals, SELV0 and SELV1, have a voltage level set by said high voltage supply at a decoder supply voltage, VSEL, said memory multiplexing signals, SELV0 and SELV1, having the highest voltage level in said memory core, wherein voltage levels of said memory multiplexing signals, SELV0 and SELV1, are set at a level low enough to avoid memory breakdowns in said memory core.

6. A method for producing two memory multiplexing signals, SELV0 and SELV1, capable of driving a large capacitive memory load comprising the steps of:

selectively decoding an address signal to determine which one of said two memory multiplexing signals, SELV0 and SELV1, is to be driven high and the other to be driven low; and

generating said two memory multiplexing signals, SELV0 and SELV1, as tristated signals, without generating any crowbar current when switching between said low and high logic levels of SELV0 and SELV1, whereby noise to ground is reduced.

7. The method of claim 6 wherein said step of generating comprises the step of controlling one FET in a pair of two large FETs coupled in series, said memory multiplexing signals, SELV0 and SELV1, being derived respectively from said coupling between one of said pair of said two large FETs, said step of controlling comprises the steps of turning each one of said two large FETs off before turning on the other one of said two large FETs in each of said pairs of FETs, so that one of said FETs of each pair will always be off when the other one of said pair of FETs is on.

8. The method of claim 7 further comprising the step of setting the voltage levels of said memory multiplexing signals, SELV0 and SELV1, by a decoder supply voltage, VSEL, said memory multiplexing signals, SELV0 and SELV1, having the highest voltage level in said memory core, wherein voltage levels of said memory multiplexing signals, SELV0 and SELV1, are set at a level low enough to avoid memory breakdowns in said memory core.

9. A driver circuit for driving a large capacitve load while avoiding crowbar currents comprising:

two large FETs coupled in series, an output signal being derived from said coupling between said two large FETs; and

means for turning each one of said two large FETs off before turning on the other one of said two large FETs, so that one of said FETs will always be off when the other one of said FETs is on so that no crowbar current is generated as said two large FETs are switched, whereby noise to around is reduced.