Processing board, a computer, and a fault recovery method for the computer
First Claim
1. A processing board including a clock signal, the processing board for connecting to at least one system bus, the processing board comprising:
- a single clock circuit supplying the clock signal;
at least three processing units, each processing unit connected to receive the clock signal and operating synchronous with the clock signal, each processing unit receiving and executing same instructions, each processing unit including a processor and each processing unit including a cache memory coupled to the processor of the processing unit, each processing unit having an output signal carrying outputs from the processor and the cache memory;
a majority unit having an input connected to each processing unit and an output connected to the system bus that receives the output signal from each processing unit, and provides a selected output signal to the system bus, the majority unit further having a control register connected to receive the selected output signal and to be written thereby with a value controlling connection status, isolation status and interrupt status for all of the processing units; and
a processor bus connecting each processing unit to the majority unit;
wherein all elements are included on a single processing board.
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Abstract
A fault recovery process of a computer is provided for removing a fault from the system as soon as possible, minimizing the secondary fault and improving the availability of the system. In a reliable computer, which includes a system bus, a main memory connected to the system bus, and at least one processing board connected to the system bus, at least one processing board executes the same instructions by n (n>=3) processing units having cache memories respectively. When one of the processing units of the processing board becomes faulty, the other processing units continue executing the processes, which are being executed by the faulty processing board, and then, the processes to be registered in the faulty processing board, are succeeded by other processing boards.
160 Citations
19 Claims
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1. A processing board including a clock signal, the processing board for connecting to at least one system bus, the processing board comprising:
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a single clock circuit supplying the clock signal; at least three processing units, each processing unit connected to receive the clock signal and operating synchronous with the clock signal, each processing unit receiving and executing same instructions, each processing unit including a processor and each processing unit including a cache memory coupled to the processor of the processing unit, each processing unit having an output signal carrying outputs from the processor and the cache memory; a majority unit having an input connected to each processing unit and an output connected to the system bus that receives the output signal from each processing unit, and provides a selected output signal to the system bus, the majority unit further having a control register connected to receive the selected output signal and to be written thereby with a value controlling connection status, isolation status and interrupt status for all of the processing units; and a processor bus connecting each processing unit to the majority unit; wherein all elements are included on a single processing board. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A recovery method for a processing board having at least three processing units each processing unit operating synchronous with a clock signal, receiving and executing same instructions, each processing unit having a processor and each processing unit having a cache memory coupled to the processor of the processing unit, the processing board having a majority unit, the majority unit coupled to each processing unit for selecting one processing unit of the at least three processing units and interfacing the one processing unit with external units, the majority unit further having a control register holding a value controlling connection and interrupt status of each of the processing units, the method comprising the steps of:
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synchronizing all processing units to a single clock signal; detecting in the majority unit a faulty processing unit; generating a first control register value in which an interrupt flag and a connect flag, each corresponding to the faulty processing unit, have values to cause operation of the faulty processor to cease; writing the first control register value to the control register causing operation of the detected faulty unit to cease; generating a second control register value in which an isolate flag has a value to cause operation of a processing unit in isolation and in which the interrupt flag and the connect flag have values to cause operation of the faulty processing unit to occur; writing the second control register value to the control register causing a self diagnosis test to execute in the faulty processing unit; generating a third control register value in which interrupt flags and connect flags corresponding to each of the at least three processing units have values to cause a synchronous start of the at least three processing unit; writing the third control register value to the control register causing the faulty processing unit to synchronize with other processing units. - View Dependent Claims (17, 18, 19)
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Specification