Decompression processor for video applications

• US 5,815,646 A
• Filed: 10/11/1994
• Issued: 09/29/1998
• Est. Priority Date: 04/13/1993
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: C-Cube Corporation (Broadcom, Inc.)
• Inventors: Purcell, Stephen C., Galbi, David E., Liao, Frank H., Tse, Yvonne C.
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/296,387
• Time in Patent Office: 1,449 Days
• Field of Search: 395/162-166, 345/185, 345/187, 345/189, 345/201, 345/202, 345/203, 348/426, 348/700, 348/721, 382/232, 382/233, 382/272
• US Class Current: 345/502
• CPC Class Codes: H03M 7/425 for the decoding process only
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/124 Quantisation
• CPC Class Codes: H04N 19/126 Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/433 characterised by techniques for memory access
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence

Abstract

A method and structure including four video decompression structures and eight memory banks are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, the 1920×1080 pixel display space is divided into four vertical sections of 480×1080 pixels. Each memory bank stores the values of pixels in one non-overlapping group of 240×1080 pixels. Each decompression structure decodes a 480×1088-pixel picture area with access to up to two additional 240×1088-pixel picture areas. The video decompression structures decode the vertical sections in lock-step to avoid the problem of the same bank of memory being accessed by more than one video decompression structure. In one embodiment of the present invention, a macroblock fetch can cross 1-4 DRAM page boundaries. So, in order to maintain the lock-step relationship of the video decompression structures, each page mode access is limited to fetching only an 8×8 quad pixel picture area, so that regardless of the number of DRAM page boundaries required to be crossed, four page mode access cycles are required for each reference macroblock fetched.

Claims

1. A structure for processing a picture area of m×

n pixels, comprising;

2r memory banks, each memory bank storing the values of pixels in one non-overlapping group of m/2r×

n pixels in said picture area, m being greater than 1; and

r processors, r being greater than 1, each accessing two associated memory banks in addition to one memory bank associated with a right neighbor if present and one memory bank associated with a left neighbor if present, each processor being responsible for processing the pixels associated with two of said accessible memory banks.

2. A structure as in claim 1, wherein each processor is associated with two neighboring processors, each neighboring processors being one of said r processors, said four memory banks being associated with a contiguous picture area of 2m/r×

n pixels, said processor being responsible for processing the pixels in the two memory banks associated with the middle portion of said 2m/r×

n pixels picture area, and said neighboring processors being each responsible for processing one of the two groups of m/2r×

n pixels on each side of said 2m/r×

n picture area.

3. A structure as in claim 1, wherein said r processors each process said contiguous picture area in lockstep.

4. A structure as in claim 3, wherein each contiguous picture area is divided into an equal number of fixed-size picture areas, each processor further comprising means for ensuring that the time required for accessing each of said fixed-size areas is substantially constant.

5. A method for processing a picture area of m×

n pixels, comprising the steps of;

providing 2r memory banks, each memory bank storing the values of pixels in one non-overlapping group of m/2r×

n pixels in said picture area, m being greater than 1; and

providing r processors, r being greater than 1, each accessing two associated memory banks in addition to one memory bank associated with a right neighbor if present and one memory bank associated with a left memory bank if present, each processor being responsible for processing the pixels associated with two of said accessible memory banks.

6. A method as in claim 5, wherein said processor providing step further comprises the step of associating each processor with two neighboring processors, each neighboring processors being one of said r processors, said four memory banks being associated with a contiguous picture area of 2m/r×

n pixels, said processor being responsible for processing the pixels in the two memory banks associated with the middle portion of said 2m/r×

n pixels picture area, and said neighboring processors being each responsible for processing one of the two groups of m/2r×

n pixels on each side of said 2m/r×

n picture area.

7. A method as in claim 5, further comprising the step of ensuring said r processors each process said contiguous picture area in lockstep.

8. A method as in claim 7, wherein each contiguous picture area is divided into an equal number of fixed-size picture areas, said method further comprising the step of ensuring that the time required for accessing each of said fixed-size areas is substantially constant.