Circuit and method for battery charge control

• US 5,818,201 A
• Filed: 03/11/1997
• Issued: 10/06/1998
• Est. Priority Date: 03/03/1995
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Stockstad, Troy Lynn, Yee, Renwin J., Petty, Thomas D.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): SHIN, KYUNG E
• Application Number:
  US08/814,684
• Time in Patent Office: 574 Days
• Field of Search: 320/5, 320/15, 320/17, 320/18, 320/130, 320/30-34, 320/39-40, 320/48, 320/47, 320/35-36, 320/118, 320/119, 320/120, 320/121, 320/122, 320/116
• US Class Current: 320/119
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits
• CPC Class Codes: H02J 7/00308 Overvoltage protection
• CPC Class Codes: H02J 7/0036 using connection detecting circuits H02J7/0034 takes precedence
• CPC Class Codes: H02J 7/007182 in response to battery voltage

Abstract

A battery charge control circuit (10) senses the charge condition of cells in a battery pack (12, 14, 16, 18) using a measurement circuit (51). Upon detection of a single under-voltage cell, the charge control circuit is placed in a sleep mode. Pack sense circuit (240) senses when the battery pack is placed in a charger. If circuit (10) was in a sleep mode, it is awakened. If any cell is measured over-voltage, the status is checked versus the other cells. If all the cells are over-voltage, the battery is considered balanced. If one or more cells are not over-voltage, a control circuit (32) activates a discharge transistor (212, 214, 216, 218), discharging the cell within a hysteresis voltage below the over-voltage limit. Charge balancing of cells is continued until the cells are within a programmable hysteresis voltage of each other.

Claims

1. A battery control circuit, comprising:

a measurement circuit that provides a status signal upoon provides voltage condition, the measurement circuit including;

a first multiplexer having a first signal input, a second signal input, a first select input, a second select input and an output, the first and second signal inputs of the first multiplexer selected in response to selection signals appearing at the first and second select inputs;

a second multiplexer having a first signal input, a second signal input, a first select input, a second select input, and an output, the first and second signal inputs of the second multiplexer selected in response to the selection signals appearing at the first and second select inputs;

a voltage divider circuit coupled between the outputs of the first and second multiplexers, the voltage divider circuit having an output node;

a comparator having first and second inputs and an output, the first input selectively coupled to the output node of the voltage divider circuit, and the output providing the status signal;

a control circuit responsive to said status signal for decoding a control signal from said status signal; and

a discharge circuit coupled between the control circuit and the first multiplexer and operating in response to said control signal.

2. The battery charge control circuit of claim 1, further including:

a first battery cell having a first terminal and a second terminal, the first terminal coupled to the first input of the first multiplexer, the second terminal coupled to the second input of the first multiplexer and to the first input of the second multiplexer; and

a second battery cell having a first terminal and a second terminal, the first terminal coupled to the second input of the first multiplexer and the second terminal coupled to the second input of the second multiplexer.

3. The battery charge control circuit of claim 2, wherein said measurement circuit is coupled for receiving a second battery voltage from said second battery cell and providing a status signal upon sensing an over-voltage condition in said second battery cell, and said control circuit is responsive to said status signal for decoding a second battery control signal from said status signal, and said discharge circuit is coupled across said second battery cell and operating in response to said second battery control signal for discharging the second battery cell and achieving a balanced condition between said first and second battery voltages.

4. The battery control circuit of claim 1, wherein the voltage divider circuit comprises:

a first resistor having first and second terminals, said first terminal coupled to said output of said first multiplexer; and

a second resistor having first and second terminals, said first terminal of said second resistor coupled to said first terminal of the first resistor and the second terminal of the second resistor coupled to the output of the second multiplexer.

5. The battery control circuit of claim 1, wherein the control signal is an over-voltage control signal.

6. The battery control circuit of claim 1, wherein the control signal is an under-voltage control signal.

7. The battery control circuit of claim 1, wherein the discharge circuit includes a first discharge transistor having a control electrode and first and second current carrying electrodes, wherein the first current carrying electrode is coupled to the first signal input of the first multiplexer, the second current carrying electrode is coupled to the second signal input of the first multiplexer, and the control electrode is coupled to the control circuit.

8. The battery control circuit of claim 7, wherein the first discharge transistor is a field effect trnansistor.

9. The batter control circuit of claim 7, wherein the discharge circuit further includes a second discharge transistor having a control electrode and first and second current carrying electrodes, wherein the first current carrying electrode is coupled to the first signal input of the first multiplexer, the second current carrying electrode is coupled to the second signal input of the first multiplexer, and the control electrode is coupled to the control circuit.

17. The battery charge control circuit of claim 4, further including:

a third resistor coupled between the first and second resistors, wherein a connection between the second and third resistors form a second node; and

a switching circuit having first and second input terminals, a control terminal, and an output terminal, said first input terminal selectively coupled to said first node, said second input terminal selectively coupled to said second node, said output terminal coupled to said first input of said comparator.

18. The battery charge control circuit of claim 17 wherein said control circuit is responsive to a system clock for generating said select signal for said first and second multiplexers.

10. A battery charge control circuit for sensing a connection of the battery cell to a battery charger, comprising:

a measurement circuit coupled for receiving a first battery voltage between first and second terminals and having an output for,providing one of a first status signal upon sensing a first voltage condition in the battery cell or a second status signal upon sensing a second voltage condition in the battery cell, the measurement circuit including;

a first multiplexer having a first signal input, a second signal input, a first select input, a second select input, and an output, the first and second signal inputs of the first multiplexer selected in response to selection signals appearing at the first and second select inputs;

a second multiplexer having a first signal input, a second signal input, a first select input, a second select input, and an output, the first and second signal inputs of the second multiplexer selected in response to the selection signals appearing at the first and second select inputs;

a voltage divider circuit coupled between the outputs of the first and second multiplexers, the voltage divider circuit having an output node;

a comparator having first and second inputs and an output, the first input selectively coupled to the output node of the voltage divider circuit, and the output providing the first status signal;

a first logic circuit having an input coupled to the output of said measurement circuit and having an output;

a second logic circuit having a first input coupled for receiving said first status signal, a second input, and an output responsive to said first status signal;

a first transistor having a gate coupled to the output of said first logic circuit, a source coupled to a third terminal, and a drain;

a second transistor having a gate coupled to the output of said second logic circuit, a drain coupled to said drain of said first transistor, and a source coupled to said second terminal; and

a detector circuit having a first input coupled to said source of said first transistor for detecting a first voltage, a second input coupled to said output of said first logic circuit, a third input coupled for detecting a voltage at said second terminal, and an output coupled to said input of said second logic circuit and responsive to a differential of said first voltage and said voltage at said second terminal for providing an activation signal.

11. The battery charge control circuit of claim 10, wherein said first voltage condition is an undervoltage condition and said second voltage condition is an overvoltage condition.

12. The battery charge control circuit of claim 11, wherein said first logic circuit comprises:

an OR gate having first and second inputs and an output;

a first flip-flop having a data input, a clock input, and an output, wherein the output of the first flip-flop is coupled to the first input of the OR gate;

a second flip-flop having a data input, a clock input, and an output, wherein the data input of the second flip-flop is coupled to the output of the first flip-flop,

a NOR gate having first and second inputs and an output;

a first transistor having a control electrode coupled to the output of the NOR gate via an inverter, and first and second current carrying electrodes;

a second transistor having a control electrode and first and second current carrying electrodes, wherein the second current carrying electrode of the second transistor is coupled to the first current carrying electrode of the first transistor;

a third transistor having a control electrode and first and second current carrying electrodes, wherein the control electrode of the third transistor is coupled to the output of the NOR gate and the second current carrying electrode of the third transistor is coupled to the second current carrying electrode of the first transistor;

a fourth transistor having a control electrode and first and second current carrying electrodes, wherein the control electrode of the fourth transistor is coupled to the second current carrying electrode of the second transistor, the second current carrying electrode of the fourth transistor is coupled to the first current carrying electrode of the third transistor, and the first current carrying electrodes of the second and fourth transistors are commonly coupled;

a fifth transistor having a control electrode coupled to the control electrode of the fourth transistor, a first current carrying electrode coupled to the first current carrying electrodes of the third and fourth transistors, and a second current carrying electrode;

a sixth transistor having a control electrode and first and second current carrying electrodes, wherein the first current carrying electrode of the sixth transistor is coupled to the second current carrying electrode of the fifth transistor;

a seventh transistor having a control electrode and first and second current carrying electrodes, wherein the control electrode of the seventh transistor is coupled to the second current carrying electrode of the fifth transistor, the second current carrying electrode of the seventh transistor is coupled to the second current carrying electrode of the sixth, and the control electrode of the sixth transistor is coupled to the first current carrying electrode of the seventh transistor;

an eighth transistor having a control electrode and first and second current carrying electrodes, wherein the control electrode of the eighth transistor is coupled to the control electrode of the second transistor, the second current carrying electrode of the eighth transistor is coupled to the first current carrying electrode of the seventh transistor, and the first current carrying electrode of the eighth transistor is coupled to the first current carrying electrode of the fifth transistor; and

a ninth transistor having a control electrode and first and second current carrying electrodes, wherein the control electrode of the ninth transistor is coupled to the control electrode of the sixth transistor, and the second current carrying electrode of the ninth transistor is coupled to the second current carrying electrode of the seventh transistor.

13. The battery charge control circuit of claim 12, wherein the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth transistors are field effect transistors.

14. The battery charge control circuit of claim 10 wherein said detector circuit further comprises:

a third transistor having a gate coupled to said output of said first logic circuit, a source, and a drain;

a fourth transistor having a base coupled to said source of said third transistor, an emitter coupled to said third terminal, and a collector;

a fifth transistor having a collector and a base coupled to said collector of said fourth transistor, and an emitter coupled to said first terminal;

a sixth transistor having a base coupled to said base of said fifth transistor, an emitter coupled to said first terminal, and a collector;

a seventh transistor having a base coupled to said base of said sixth transistor, an emitter coupled to said first terminal, and a collector;

an eighth transistor having a collector and a base coupled to said collector of said seventh transistor, and an emitter coupled to said second terminal;

a ninth transistor having a base coupled to said base of said eighth transistor, an emitter coupled to said second terminal, and a collector coupled to said collector of said sixth transistor;

a tenth transistor having a base coupled to said collector of said ninth transistor, an emitter coupled to said third terminal, and a collector coupled to said first terminal; and

an eleventh transistor having a gate coupled to said second terminal, a source coupled to said third terminal, and a drain coupled to said first terminal.

15. The battery charge control circuit of claim 14 wherein said detector circuit further comprises:

a first resistor having a first terminal coupled to said emitter of said ninth transistor and a second terminal coupled to said second terminal of said detector circuit;

a second resistor having a first terminal coupled to said emitter of said fourth transistor and a second terminal coupled to said third terminal of said detector circuit;

a third resistor having a first terminal coupled to said collector of said tenth transistor and a second terminal coupled to said first terminal of said detector circuit; and

a fourth resistor having a first terminal coupled to said drain of said eleventh transistor and a second terminal coupled to said first terminal of said detector circuit.

16. The battery control circuit of claim 10, wherein the voltage divider circuit comprises:

a

first resistor having first and second terminals, said first terminal coupled to said output of said first multiplexer; and

a second resistor having first and second terminals, said first terminal of said second resistor coupled to said first terminal of the first resistor and the second terminal of the second resistor coupled to the output of the second multiplexer.

19. A method of charging cells of a battery, comprising the steps of:

multiplexing first and second cells of the battery with a selection signal to produce a first terminal voltage of a selected cell at a first node while concurrently producing a second terminal voltage of the selected cell at a second node with the selection signal;

subtracting the second terminal voltage from the first terminal voltage to produce a difference signal; and

comparing the difference signal to a reference signal to produce a charge control signal representative of a charge of the selected cell.

20. The method of claim 19, further comprising the step of discharging the selected cell in response to the charge control signal.

21. The method of claim 19, wherein the step of subtracting includes the step of voltage dividing the first and second selected potentials to produce the difference signal.

22. A circuit for charging battery cells, comprising:

a multiplexer having a first input coupled across a first battery cell and a second input coupled across a second battery cell, and selecting between the first and second battery cells with a selection signal to provide a potential of a selected cell across first and second outputs; and

a comparator having a first input coupled for receiving the potential of the selected cell, a second input coupled for receiving a reference signal and an output for providing a charge control signal representative of a charge of the selected cell.

23. The circuit of claim 22, further comprising:

a first discharge circuit having an enable input coupled for receiving the selection signal and first and second terminals coupled for discharging the first battery cell when the charge control signal is in a first state; and

a second discharge circuit having an enable input coupled for receiving the selection signal and first and second terminals coupled for discharging the second battery cell when the charge control signal is in a second state.

24. The circuit of claim 23, further comprising a voltage divider having first and second inputs coupled to the first and second outputs of the multiplexer, and an output coupled to the first input of the comparator.