Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit

• US 5,818,289 A
• Filed: 07/18/1996
• Issued: 10/06/1998
• Est. Priority Date: 07/18/1996
• Status: Expired due to Term

• Current Assignee: Micron Quantum Devices Inc (Micron Technology, Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Chevallier, Christophe J., Lakhani, Vinod C.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ADOLPHE, EUNJA
• Application Number:
  US08/683,474
• Time in Patent Office: 810 Days
• Field of Search: 327/331, 327/332, 327/536, 327/537, 327/540, 327/541, 327/543, 327/544, 327/534, 365/226
• US Class Current: 327/536
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

An efficient charge pump circuit. Increased efficiency compared to previous pump circuits is achieved through use of a novel charge transfer switch and associated clocking scheme which reduces the supply current required to operate the charge pump. Instead of repeatedly charging and discharging a stray capacitance of each pump stage capacitor, some of the charge stored in the stray capacitor on the clock driver side is transferred to the next pump stage. This serves to pre-charge the stray capacitor of the next stage, reducing the supply current required to operate the charge pump. The apparatus and method described can also be used to reduce the power consumed by a system or circuit which has internal signals or nodes which are in opposite phase to each other. This is accomplished by reducing the power used to charge and discharge a stray capacitance associated with the signals or nodes.

Claims

1. A charge pump for transforming an input voltage to an output voltage, comprising:

a first and a second pump stage, wherein each pump stage includes a stage capacitor which is charged and discharged during a clock cycle of the charge pump, clock drivers coupled to the stage capacitor on a clock driver side of said stage capacitor and configured to control charging and discharging of the stage capacitor in response to clock signals, and wherein the stage capacitor has an associated stray capacitance on the clock driver side; and

a charge transfer switch connected to the clock driver side of the first pump stage which electrically connects the stray capacitance of the first pump stage on the clock driver side to the stray capacitance on the clock driver side of the second pump stage in response to a control signal, thereby transferring charge between the stray capacitance of the first pump stage and the stray capacitance of the second pump stage.

2. The charge pump of claim 1, further comprising:

a control signal generator which generates the control signal.

3. The charge pump of claim 1, wherein each of the first and second pump stages further comprises:

a diode connected between the stage capacitor and an input voltage for the pump stage, wherein the diode prevents discharging of the stage capacitor.

4. The charge pump of claim 3, wherein the diode is a properly configured transistor.

5. The charge pump of claim 4, wherein the diode has an associated voltage drop across it equal to the threshold voltage of the transistor, and each of the first and second pump stages further comprises:

a threshold voltage canceler which compensates for the voltage drop across the diode.

6. The charge pump of claim 1, wherein the charge transfer switch is a transistor which is electrically connected between the stray capacitance on the clock driver side of the stage capacitor of the first pump stage and the stray capacitance on the clock driver side of the stage capacitor of the second pump stage.

7. A charge pump for transforming an input voltage to an output voltage, comprising:

a pump circuit having an input and an output;

a clock signal generator which generates a plurality of clock signals used to control operation of the pump circuit, wherein the input of the pump circuit receives an input supply voltage and the clock signals generated by the clock signal generator, and the output of the pump circuit asserts a transformed input supply voltage, and wherein the pump circuit comprises

a first and a second pump stage, wherein each pump stage includes a stage capacitor which is charged and discharged during a clock cycle of the charge pump, first and second clock drivers coupled to the stage capacitor on a clock driver side of the stage capacitor and configured to control charging and discharging of the stage capacitor in response to first and second clock signals, and wherein the stage capacitor has an associated stray capacitance on the clock driver side; and

a charge transfer switch connected to the clock driver side of the first pump stage which electrically connects the stray capacitance of the first pump stage and the stray capacitance of the second pump stage upon receipt of one of the clock signals generated by the clock signal generator, thereby transferring charge between the stray capacitance of the first pump stage and the stray capacitance of the second pump stage.

8. The charge pump of claim 7, further comprising:

a regulator having an input and an output, wherein the input of the regulator is couple to the output of the pump circuit and the output of the regulator asserts a control signal which acts to vary the output of the clock signal generator.

9. The charge pump of claim 7, wherein each of the first and second pump stages which are part of the pump circuit further comprises:

a diode connected between the stage capacitor and an input voltage for the pump stage, wherein the diode prevents discharging of the stage capacitor.

10. The charge pump of claim 9, wherein the diode is a properly configured transistor.

11. The charge pump of claim 10, wherein the diode has an associated voltage drop across it equal to the threshold voltage of the transistor, and each of the first and second pump stages further comprises:

a threshold voltage canceler which compensates for the voltage drop across the diode.

12. The charge pump of claim 7, wherein the charge transfer switch is a transistor which electrically connects the stray capacitance of the first pump stage and the stray capacitance of the second pump stage.

13. A charge pump for transforming an input voltage to an output voltage, comprising:

a first and a second pump stage, wherein each pump stage includes a stage capacitor which is charged and discharged during a clock cycle of the charge pump, first and second clock drivers coupled to the stage capacitor on a clock driver side of the stage capacitor and configured to control charging and discharging of the stage capacitor in response to first and second clock signals, and wherein the stage capacitor has an associated stray capacitance on the clock driver side; and

a charge transfer switch connected to the clock driver side of the first pump stage which electrically connects the stray capacitance of the first pump stage to the stray capacitance of the second pump stage upon receipt of a control signal, thereby transferring charge between the stray capacitance of the first pump stage and the stray capacitance of the second pump stage.

14. The charge pump of claim 13, further comprising:

a control signal generator which generates the control signal.

15. The charge pump of claim 13, wherein each of the first and second pump stages further comprises:

a diode for preventing discharging of the stage capacitor.

16. The charge pump of claim 15, wherein the diode is a properly configured transistor.

17. The charge pump of claim 16, wherein the diode has an associated voltage drop across it equal to the threshold voltage of the transistor, and each of the first and second pump stages further comprises:

a threshold voltage canceler which compensates for the voltage drop across the diode.

18. The charge pump of claim 13, wherein the charge transfer switch is a transistor which electrically connects the stray capacitance of the first pump stage and the stray capacitance of the second pump stage.

19. A method of operating a charge pump to transform an input voltage to an output voltage, the charge pump comprising pump stages, each of the pump stages including a stage capacitor which is charged and discharged during a clock cycle, clock drivers coupled to the stage capacitor on a clock driver side of the stage capacitor and configured to control charging and discharging of the stage capacitor in response to clock signals wherein the stage capacitor has an associated stray capacitance on the clock driver side, said method comprising the steps of:

charging the pump stage capacitor and the stray capacitance on the clock driver side of a first one of the pump stages to a predetermined voltage level;

electrically connecting the stray capacitance on the clock driver side of the first one of the pump stages to the stray capacitance on the clock driver side of a second one of the pump stages, thereby transferring charge between the stray capacitance of the first one of the pump stages and the stray capacitance of the second one of the pump stages; and

charging the pump stage capacitor of the second one of the pump stages to a predetermined voltage level.

20. The method of claim 19, wherein the step of electrically connecting the stray capacitance of the first pump stage to a stray capacitance of a second pump stage further comprises:

generating a control signal for operating a charge transfer switch which electrically connects the stray capacitance of the first pump stage to the stray capacitance of the second pump stage.

21. A charge pump for transforming an input voltage to an output voltage, comprising:

a first pump stage, wherein the first pump stage includes a first stage capacitor which is charged and discharged during a clock cycle of the charge pump, first and second first stage clock drives coupled to the first stage capacitor on a clock driver side of the first stage capacitor and configured to control charging and discharging of the first stage capacitor in response to first and second first stage clock signals, and wherein the the first stage capacitor has an associated first stage capacitance on the clock driver side of the first pump stage;

a second pump stage, wherein the second pump stage includes a second stage capacitor which is charged and discharged during a clock cycle of the charge pump, first and second stage clock drives the second stage capacitor on a clock driver side of the second stage capacitor and configured to control charging and discharging of the second stage capacitor in response to first and second second stage clock signals, and wherein the second stage capacitor has an associated second stage stray capacitance on the clock driver side of the second pump stage;

a charge transfer switch connected to the clock driver side of the first pump stage which electrically connects the first stage stray capacitance on the clock driver side of the first pump stage to the second stage stray capacitance on the clock driver side of the second pump stage in response to a control signal, thereby transferring charge between the first stage capacitance and the second stage stray capacitance; and

a control signal generator which generates the control signal.

22. The charge pump of claim 21, wherein each of the first and second pump stages further comprises:

a diode connected between the stage capacitor and an input voltage for the pump stage, wherein the diode prevents discharging of the stage capacitor.

23. The charge pump of claim 22, wherein the diode is a properly configured transistor.

24. The charge pump of claim 23, wherein the diode has an associated voltage drop across it equal to the threshold voltage of the transistor, and each of the first and second pump stages further comprises:

a threshold voltage canceler which compensates for the voltage drop across the diode.

25. The charge pump of claim 21, wherein the charge transfer switch is a transistor which is electrically connected between the first stage stray capacitance on the first stage clock drivers side and the second stage stray capacitance on the second stage clock drivers side.

26. The charge pump of claim 21, wherein the first and second first stage clock signals are not at the same time.

27. The charge pump of claim 21, wherein the first and second second stage clock signals are not active at the same time.

30. The charge pump of claim 21, wherein the control signal is not active when any of the first or second first stage clock signals and first or second second stage clock signals are active.

28. A charge pump for transforming an input voltage to an output voltage, comprising:

a first pump stage, wherein the first pump stage includes a first stage capacitor which is charged and discharged during a clock cycle of the charge pump and first and second first stage clock drivers which drive first and second first stage clock signals used to operate the first stage capacitor, and wherein the first stage capacitor has an associated first stage stray capacitance on the first stage clock drivers side;

a second pump stage, wherein the second pump stage includes a second stage capacitor which is charged and discharged during a clock cycle of the charge pump and first and second second stage clock drivers which drive first and second second stage clock signals used to operate the second stage capacitor, and wherein the second stage capacitor has an associated second stage stray capacitance on the second stage clock drivers side;

a charge transfer switch which electrically connects the first stage stray capacitance on the first stage clock drivers side to the second stage stray capacitance on the second stage clock drivers side upon receipt of a control signal, thereby transferring charge between the first stage stray capacitance and the second stage stray capacitance; and

a control signal generator which generates the control signal, wherein the first first stage clock driver is an n-channel device and the second first stage clock driver is a p-channel device.

29. A charge pump for transforming an input voltage to an output voltage, comprising:

a first pump stage, wherein the first pump stage includes a first stage capacitor which is charged and discharged during a clock cycle of the charge pump and first and second first stage clock drivers which drive first and second first stage clock signals used to operate the first stage capacitor, and wherein the first stage capacitor has an associated first stage stray capacitance on the first stage clock drivers side;

a second pump stage, wherein the second pump stage includes a second stage capacitor which is charged and discharged during a clock cycle of the charge pump and first and second second stage clock drivers which drive first and second second stage clock signals used to operate the second stage capacitor, and wherein the second stage capacitor has an associated second stage stray capacitance on the second stage clock drivers side;

a charge transfer switch which electrically connects the first stage stray capacitance on the first stage clock drivers side to the second stage stray capacitance on the second stage clock drivers side upon receipt of a control signal, thereby transferring charge between the first stage stray capacitance and the second stage stray capacitance; and

a control signal generator which generates the control signal, wherein the first second stage clock driver is an n-channel device and the second second stage clock driver is a p-channel device.

31. A low power consumption system, comprising:

a first signal driver having a first capacitor, a first output, and first driver on a clock driver side of the first capacitor, said first driver configured to control charging and discharging of the first capacitor in response to a first set of clock signals, wherein the first signal driver is configured to assert a first signal at the first output, and wherein there is a first stray capacitance on the clock driver side of the first capacitor;

a second signal driver having a second capacitor, a second output, and a second driver on a clock driver side of the second capacitor, said second driver configured to control charging and discharging of the second capacitor in response to a second set of clock signals, wherein the second signal driver is configured to assert a second signal at the second output, wherein the first signal and the second signal are in opposite phase to each other, and wherein there is a second stray capacitance on the clock driver side of the second capacitor; and

a charge transfer switch connected to the clock driver side of the first signal driver, which electrically connects the first stray capacitance to the second stray capacitance upon receipt of a control signal, thereby transferring charge between the first and second stray capacitances.

32. The system of claim 31 further comprising:

a control signal generator which generates the control signal.