Decoding video signals at high speed using a memory buffer

• US 5,818,468 A
• Filed: 06/04/1996
• Issued: 10/06/1998
• Est. Priority Date: 06/04/1996
• Status: Expired due to Term

• Current Assignee: V-Silicon Semiconductors (HEFEI) Co., Ltd.
• Original Assignee: Sigma Designs Incorporated
• Inventors: Fraenkel, Bernard G., Nguyen, Julien T., Le Cornec, Yann
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/658,994
• Time in Patent Office: 854 Days
• Field of Search: 345/501, 345/502, 345/507, 345/509, 345/520, 345/521, 345/202, 345/515, 345/516, 711/100, 711/111, 711/150, 711/151, 348/513, 348/514, 348/497, 348/714-716, 348/718
• US Class Current: 345/535
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer

Abstract

A method for decoding and displaying video signals using a memory buffer, in which a speed of a write operation for a memory buffer is adjusted to avoid overtaking a read operation for the same memory buffer. A display controller and a video MPEG engine contend for access to a DRAM memory buffer controller, and have their relative priorities set so that the video MPEG engine operates to write to the memory buffer at a relatively slow speed during a time period when the display controller is reading from that same memory buffer, and to write to the memory buffer at a relatively fast speed during a time period when the display controller is not reading from the memory buffer. The relatively slow speed is preferably much slower than the reading speed of the display controller, while the relatively fast speed is preferably much faster than the display controller. The DRAM memory buffer controller has a limited memory transfer bandwidth; the display controller and the video MPEG engine are operated at speeds which completely occupy that bandwidth, with the display controller given higher priority. Thus, while the display controller is reading from the memory buffer, the video MPEG engine is constrained to operate at a relatively slow speed, and is unable to overtake the display controller, but while the display controller is not reading from the memory buffer (e.g., during a vertical retrace interval), the video MPEG engine is able to operate at a relatively high speed, and is able to write an entire frame to the memory buffer in a relatively short time.

Claims

1. A system for decoding and displaying video signals, said system comprising

a memory;

a memory controller coupled to said memory;

a display controller coupled to said memory controller; and

a video MPEG engine coupled to said memory controller;

wherein said display controller and said video MPEG engine contend for access to said memory controller, and have relative priorities set so that said video MPEG engine operates to write to the memory buffer at a relatively slow speed during a time period when said display controller is reading from said memory buffer, and said video MPEG engine operates to write to said memory buffer at a relatively fast speed during a time period when said display controller is not reading from said memory buffer.

2. A system as in claim 1, wherein said relatively slow speed is slower than a reading speed of said display controller, and said relatively fast speed is faster than said reading speed.

3. A system as in claim 1, wherein

said memory controller has a limited memory transfer bandwidth;

and

said display controller and said video MPEG engine are operated at speeds which completely occupy said transfer bandwidth, with said display controller given higher priority.

4. A system as in claim 1, wherein said video MPEG engine operates to decode and write a full frame to said memory buffer during each frame time.

5. A system for decoding and displaying video signals, said system comprising

a memory, and a memory controller coupled to said memory;

a display controller coupled to said memory controller and coupled to a read pointer for said memory;

a video MPEG engine coupled to said memory controller and coupled to a write pointer for said memory; and

means for controlling said video MPEG engine so that said write pointer advances more slowly than said read pointer for a first part of, a plurality of frame times, advances more quickly than said read pointer for a second part of said plurality of frame times, advances more slowly than said read pointer for a third part of said plurality of frame times.

6. A system as in claim 5, wherein said write pointer advances at least three times more quickly than said read pointer for said second part of said plurality of frame times.

7. A system as in claim 5, wherein said first part of said plurality of frame times correspond to times when said display controller is reading from said memory.

8. A system as in claim 5, wherein said second part of said plurality of frame times correspond to times when said display controller is not reading from said memory.

9. A system as in claim 5, wherein said third part of said plurality of frame times correspond to times when said display controller is reading from said memory.

10. A method for decoding and displaying video signals, said method comprising the steps of

coupling a display controller and a video MPEG engine to a memory controller for a memory;

setting relative priorities for said display controller and said video MPEG engine so that when said display controller and said video MPEG engine contend for access to said memory controller, said video MPEG engine operates to write to the memory buffer at a relatively slow speed during a time period when said display controller is reading from said memory buffer, and said video MPEG engine operates to write to said memory buffer at a relatively fast speed during a time period when said display controller is not reading from said memory buffer.

11. A method as in claim 10, wherein said relatively slow speed is slower than a reading speed of said display controller, and said relatively fast speed is faster than said reading speed.

12. A method as in claim 10, comprising the steps of

operating said display controller and said video MPEG engine at such speeds that said display controller and said video MPEG engine collectively occupy substantially all of a limited memory transfer bandwidth available from said memory controller;

and

setting a priority of said display controller higher than a priority of said video MPEG engine.

13. A method as in claim 10, comprising the step of operating said video MPEG engine to decode and write a full frame to said memory buffer during each frame time.

14. A method for decoding and displaying video signals, said method comprising the steps of

coupling a memory controller to a memory;

coupling a display controller to said memory controller and to a read pointer for said memory;

coupling a video MPEG engine to said memory controller and to a write pointer for said memory; and

controlling said video MPEG engine so that said write pointer advances more slowly than said read pointer for a first part of a plurality of frame times, advances more quickly than said read pointer for a second part of said plurality of frame times, advances more slowly than said read pointer for a third part of said plurality of frame times.

15. A method as in claim 14, wherein said write pointer advances at least three times more quickly than said read pointer for said second part of said plurality of frame times.

16. A method as in claim 14, wherein said first part of said plurality of frame times correspond to times when said display controller is reading from said memory.

17. A method as in claim 14, wherein said second part of said plurality of frame times correspond to times when said display controller is not reading from said memory.

18. A method as in claim 14, wherein said third part of said plurality of frame times correspond to times when said display controller is reading from said memory.