Dynamic memory word line driver scheme

  • US 5,822,253 A
  • Filed: 08/16/1995
  • Issued: 10/13/1998
  • Est. Priority Date: 04/06/1990
  • Status: Expired due to Term
First Claim
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1. A dynamic random access memory (DRAM) comprising:

  • (a) word lines,(b) memory cells, each comprising a charge storage capacitor and a series pass transistor for storing a Vdd logic level on the storage capacitor, the series pass transistor having an enable input connected to a word line,(c) means for receiving word line decoding signals for providing a select signal at Vdd logic levels, the Vdd logic levels having a Vdd voltage difference between logic levels,(d) a high voltage power supply Vxx which supplies a voltage for a Vxx voltage difference between logic levels which exceeds Vdd,(e) translating means connected to said receiving means and supply Vxx for translating said select signals at said Vdd logic levels to said Vxx logic levels and for applying Vxx logic levels to said word lines for application to said enable inputs, the translating means being set and reset only by Vdd logic level signals and being devoid of voltage boost capacitor.

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