Multiple parallel digital data stream channel controller architecture

  • US 5,822,553 A
  • Filed: 03/13/1996
  • Issued: 10/13/1998
  • Est. Priority Date: 03/13/1996
  • Status: Expired due to Term
First Claim
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1. A channel controller providing for the concurrent transfer of multiple parallel digital data stream between a host processor system and a plurality of I/O devices, said channel controller comprising:

  • a) a data and control bus;

    b) a first interface including a first buffer coupleable to a host processor system, said first interface providing for the transfer of first data segments, including a variable number of bytes of data up to a first predetermined plurality of bytes, between said host processor system and said first buffer and between said first buffer and said data and control bus;

    c) a second interface including a second buffer coupleable to a first predetermined I/O device, said second interface providing for the transfer of second data segments, including a variable number of bytes of data up to a second predetermined plurality of bytes, between said first predetermined I/O device and said second buffer and between said second buffer and said data and control bus;

    d) a FIFO pool coupled to said data and control bus to exchange first data segments with said first interface and second data segments with said second interface, said FIFO pool permitting the transient concurrent storage of pluralities of said first and second data segments, said FIFO pool further including an access arbiter that operates to selectively grant respective access to said FIFO pool by said first and second interfaces, said FIFO pool including a plurality of data FIFOs and wherein a first predetermine data FIFO is associate with said first and second interfaces to provide a data transfer path through said first predetermined data FIFO and between said first and second interfaces; and

    e) a third interface including a third buffer coupleable to a second predetermined I/O device, said third interface providing for the transfer of third data segments, consisting of a variable number of bytes of data up to a third predetermined plurality of bytes, between said host processor system and said third buffer and between said third buffer and said data and control bus, and wherein said access arbiter operates to selectively grant respective access to said FIFO pool by said third interface.

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