Amplifier-less low power switched-capacitor techniques

• US 5,825,230 A
• Filed: 08/22/1997
• Issued: 10/20/1998
• Est. Priority Date: 02/01/1996
• Status: Expired due to Term

• Current Assignee: University of Waikato
• Original Assignee: University of Waikato
• Inventors: Chen, Feng, Leung, Bosco
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US08/916,530
• Time in Patent Office: 424 Days
• Field of Search: 307/110, 327/536, 327/537, 327/551, 327/552, 327/554, 327/558, 327/336, 327/337
• US Class Current: 327/337
• CPC Class Codes: G06G 7/1865 with initial condition setting
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

A switched-capacitor gain-boost network includes a bank of N-substantially identical sampling capacitors connectable to an output node. An integrating capacitor has one node connected to a low potential node and a second node connected to the output node. The integrating capacitor is connected to the bank of sampling capacitors in parallel when the bank of sampling capacitors is connected to the output node. Sampling period switches are actuable during a sampling period to connect the sampling capacitors of the bank in parallel and to connect the bank between an analog signal input node and a low potential node to charge the sampling capacitors. Integrating period switches are actuable during an integrating period to connect the sampling capacitors of the bank in series and to connect the bank between a low potential node and the output node to dump the charge stored by the sampling capacitors onto the integrating capacitor. A method of providing dc gain to an analog input signal is also provided.

Claims

1. A switched-capacitor gain-boost network comprising:

a plurality of sampling charge storing devices having substantially similar charge storing characteristics, said plurality of sampling charge storing devices being connectable to an output node;

an integrating charge storing device connected to said output node and connectable to said plurality of sampling charge storing devices in parallel; and

switch means actuable during a sampling period to connect each of said sampling charge storing devices in parallel and between an analog signal input node and a first node and actuable during an integrating period to connect each of said sampling charge storing devices in series and between a low potential node and said output node wherein during said sampling period said switch means is actuated to inhibit injection charge errors from being applied to said integrating charge storage device by said sampling charge storage devices and wherein during said integrating period said switch means is actuated to inhibit voltage add-up from occurring across said sampling charge storage devices.

2. A switched-capacitor gain-boost network as defined in claim 1 wherein said switch means connects said sampling charge storing devices to said analog signal input node in a manner such that said switched-capacitor gain-boost network generates inverted output.

3. A switched-capacitor gain-boost network as defined in claim 1 wherein said switch means is also actuated during said integrating period to inhibit charge errors generated by said switch means from being applied to said integrating charge storage device.

4. A switched-capacitor gain-boost network as defined in claim 1 wherein said switch means connects said sampling charge storing devices to said analog signal input node in a manner such that said switched-capacitor gain-boost network generates non-inverted output.

5. A switched-capacitor gain-boost network as defined in claim 1 wherein said switch means is in the form of a plurality of first switches actuable during said sampling period and a plurality of second switches actuable during said integrating period, said first and second switches being responsive to clock signals to move between open and closed conditions.

6. A switched-capacitor gain-boost network as defined in claim 5 wherein said clock signals have sharp falling edges.

7. A switched-capacitor lowpass filter comprising:

a bank of substantially identical sampling capacitors Cr₁ to Cr_N connectable to an output node;

an integrating capacitor connected between said output node and a low potential node, said integrating capacitor being connectable in parallel with said bank of sampling capacitors;

a plurality of first switches actuable during a sampling period to connect the sampling capacitors of said bank in parallel and to connect said bank between an analog signal input node and a first node to charge each of said sampling capacitors; and

a plurality of second switches actuable during an integrating period to connect the sampling capacitors of said bank in series and to connect said bank between a low potential node and said output node wherein after said sampling period, the first switch connecting said sampling capacitor Cr_N to said analog signal input node is opened prior to opening the remaining first switches and wherein during said integrating period, the second switch connecting said sampling capacitor Cr_N to said output node is closed prior to closing the remaining second switches.

8. A switched-capacitor lowpass filter as defined in claim 7 wherein said plurality of first switches connects said sampling capacitors to said analog signal input node in a manner such that said switched-capacitor lowpass filter generates inverted output.

9. A switched-capacitor lowpass filter as defined in claim 7 wherein said plurality of first switches connects said sampling capacitors to said analog signal input node in a manner such that said switched-capacitor lowpass filter generates non-inverted output.

10. A switched-capacitor lowpass filter as defined in claim 7 wherein said plurality of first and second switches are responsive to clock signals having sharp falling edges.

11. A method of providing dc gain to an analog input signal comprising the steps of:

(i) during a sampling period, connecting a plurality of substantially identical sampling capacitors in parallel and charging each of said sampling capacitors; and

(ii) during an integrating period isolating said sampling capacitors from said analog input signal;

connecting said sampling capacitors in series; and

connecting the series-connected sampling capacitors to an output node and in parallel with an integrating capacitor wherein during said sampling period said sampling capacitors are isolated from said analog input signal in a manner to inhibit injection charge errors from being applied to said integrating capacitor by said sampling capacitors and wherein during said integrating period said sampling capacitors are connected in series and to said output node in a manner to inhibit voltage add-up from occurring across said sampling capacitors.

12. The method of claim 11 wherein after said sampling period the sampling capacitor connected directly to said output node is isolated from said analog input signal prior to the remaining sampling capacitors and wherein during said integrating period the sampling capacitor is connected directly to said output node before said sampling capacitors are connected in series.

13. An amplifierless switched-capacitor network comprising:

a plurality of generally identical sampling capacitors Cr₁ to Cr_N, one of said sampling capacitors Cr_N being connectable to an output node by way of a first switch and to a low potential node by way of a second switch;

an integrating capacitor connected to said output node and to ground;

a plurality of third switches actuable during a sampling period to connect said sampling capacitors in parallel;

a plurality of fourth switches actuable during an integrating period to connect said sampling capacitors in series; and

timing circuitry to apply clock signals to said first, second, third and fourth switches to actuate said switches between open and closed conditions wherein during said sampling period, said timing circuitry actuates said third switches to connect said sampling capacitors Cr₁ to Cr_N-1 to an analog signal input node and to a dc node and actuates said second switch to connect said sampling capacitor Cr_N to said analog signal input node and to said low potential node;

following said sampling period, said timing circuitry actuates said second switches to isolate sampling capacitor Cr_N from said analog signal input node and said low potential node prior to actuating said second switches to isolate said sampling capacitors Cr₁ to Cr_N-1 from said analog signal input node and dc node; and

during said integrating period, said timing circuitry actuates said first switch to connect said sampling capacitor Cr_N to said output node prior to actuating said fourth switches to connect said sampling capacitors in series.

14. An amplifierless switched-capacitor network as defined in claim 13 where said clock signals have sharp falling edges.