MOS four-quadrant multiplier including the voltage-controlled-three-transistor V-I converters

• US 5,825,232 A
• Filed: 05/16/1997
• Issued: 10/20/1998
• Est. Priority Date: 06/13/1994
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kimura, Katsuji
• Primary Examiner(s): CUNNINGHAM, TERRY D
• Application Number:
  US08/857,819
• Time in Patent Office: 522 Days
• Field of Search: 327/356, 327/357, 327/358, 327/359, 327/560, 327/563
• US Class Current: 327/356
• CPC Class Codes: G06G 7/164 using means for evaluating powers, e.g. quarter square multiplier evaluating powers G06G7/20

Abstract

A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to the product of first and second differential input voltages has first and second two-quadrant multipliers each having a differential output. The combined differential output current includes a plurality of differential output currents. First and second two-quadrant multipliers included in the MOS four-quadrant multiplier each have first and second pairs of transistors including sources connected in common to each other. A third pair of transistors is connected in cascode to the first pair of transistors as a load on the first pair of transistors. In each of the two-quadrant multipliers, the second pair of transistors has drains which are not connected in common to drains of the third pair of transistors. The second pair of transistors has gates respectively connected to drains of said first pair of transistors and sources of said third pair of transistors. The third pair of transistors of each of the first and second two-quadrant multipliers have gates connected in common to each other at a node. Each differential output current generated in a corresponding one of the first and second two-quadrant multipliers includes at least a drain current of the second pair of transistors. The differential outputs of the first and second two-quadrant multipliers are connected to each other to output the combined differential output current. The first differential input voltage is applied between the gates of the first pair of transistors, and the second differential input voltage is applied between the node of the first two-quadrant multiplier and the node of the second two-quadrant multiplier.

Claims

1. A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to a product of first and second differential input voltages, said combined differential output current including a plurality of differential output currents, said MOS four-quadrant multiplier comprising:

first and second two-quadrant multipliers each having a differential output;

each of said first and second two-quadrant multipliers having first and second pairs of transistors having sources connected in common to each other, and a third pair of transistors connected in cascode to the first pair of transistors as a load on the first pair of transistors;

said second pair of transistors of said first two-quadrant multiplier each having drains which are directly connected in common to a corresponding drain of said second pair of transistors in said second two-quadrant multiplier, said second pair of transistors having gates respectively connected to drains of said first pair of transistors and sources of said third pair of transistors in each of said first and second two-quadrant multipliers, said third pair of transistors of each of said first and second two-quadrant multipliers having gates connected in common to each other at an input voltage node in each of said first and second two-quadrant multipliers, wherein each differential output current of said plurality of differential output currents, which is generated in one of said first and second two-quadrant multipliers, comprises at least a drain current of said second pair of transistors included in said one of said first and second two-quadrant multipliers;

said differential outputs of said first and second two-quadrant multipliers being provided to supply said combined differential output current;

wherein drains of all of said third pairs of transistors of said first and second two-quadrant multipliers are directly connected in common at a first node;

wherein said first differential input voltage is applied between the gates of said first pair of transistors in each of said first and second two-quadrant multipliers; and

wherein said second differential input voltage is applied between the input voltage node of said first two-quadrant multiplier and the input voltage node of said second two-quadrant multiplier.

3. The MOS four-quadrant multiplier according to claim 1, wherein a power supply voltage is applied to the drains of the third pair of transistors in each of said first and second two-quadrant multipliers.

4. The MOS four-quadrant multiplier according to claim 1, further comprising a current mirror circuit for converting said combined differential output current into a single-ended output current.

2. A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to a product of first and second differential input voltages, said combined differential output current including a plurality of differential output currents, said MOS four-quadrant multiplier comprising:

first and second two-quadrant multipliers each having a differential output;

each of said first and second two-quadrant multipliers including first and second pairs of transistors having sources connected in common to each other, and a third pair of transistors connected in cascode to the first pair of transistors as a load on the first pair of transistors;

said second pair of transistors having gates respectively connected to drains of said first pair of transistors and sources of said third lair of transistors in each of said first and second two-quadrant multipliers, said third pair of transistors of each of said first and second two-quadrant multipliers having gates connected in common to each other at a node in each of said first and second two-quadrant multipliers;

wherein a drain of a first transistor of said second pair of transistors in said first two-quadrant multiplier is directly connected in common at a first node to a drain of a first transistor of said third pair of transistors in said first two-quadrant multiplier, said first transistor of said second pair of transistors in said first two-quadrant multiplier including a gate which is directly connected in common to a source of said first transistor of said third pair of transistors in said first two-quadrant multiplier;

wherein a drain of a second transistor of said second pair of transistors in said first two-quadrant multiplier is directly connected in common at a second node to a drain of a second transistor of said third pair of transistors in said first two-quadrant multiplier, said second transistor of said second pair of transistors in said first two-quadrant multiplier including a gate which is directly connected in common to a source of said second transistor of said third pair of transistors in said first two-quadrant multiplier;

wherein a drain of a first transistor of said second pair of transistors in said second two-quadrant multiplier is directly connected at a third node to a drain of a first transistor of said third pair of transistors in said second two-quadrant multiplier, said first transistor of said second pair of transistors in said second two-quadrant multiplier including a gate which is directly connected in common to a source of said first transistor of said third pair of transistors in said second two-quadrant multiplier, said first and third nodes being directly connected in common;

wherein a drain of a second transistor of said second pair of transistors in said second two-quadrant multiplier is directly connected in common at a fourth node to a drain of a second transistor of said third pair of transistors in said second two-quadrant multiplier, said second transistor of said second pair of transistors in said second two-quadrant multiplier including a gate which is directly connected in common to a source of said second transistor of said third pair of transistors in said second two-quadrant multiplier, said second and fourth nodes being directly connected in common;

wherein each differential output current of said plurality of differential output currents, which is generated in a corresponding one of said first and second two-quadrant multipliers, comprises at least a drain current of said second pair of transistors included in said one of said first and second two-quadrant multipliers;

said differential outputs of said first and second two-quadrant multipliers forming said combined differential output current;

wherein said first differential input voltage is applied between the gates of said first pair of transistors in each of said first and second two-qauadrant multipliers; and

wherein said second differential input voltage is applied between the node of said first two-qauadrant multiplier and the node of said second two-quadrant multiplier.

5. A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to a product of first and second differential input voltages, comprising:

first and second variable-gain cells for generating a differential output current at a gain depending on an applied tuning voltage in response to a first differential input voltage applied thereto;

each of said first and second variable-gain cells comprising a tail current source, first and second pairs of transistors having sources connected in common to each other and to said tail current source, and a third pair of transistors connected in cascade to the first pair of transistors as a load on the first pair of transistors;

said second pair of transistors having gates connected to drains of said first pair of transistors in each of said first and second variable-gain cells, said third pair of transistors in said first variable gain cell including transistors having gates which are connected in common to respective gates of the transistors of the third pair of transistors in said second variable cell at first and second nodes for applying the tuning voltage therebetween, said first pair of transistors of said first and second variable gain cells having gates for applying the first differential input voltage therebetween in each of said first and second variable-gain cells, said differential output current containing at least drain currents of the second pair of transistors;

said first and second variable-gain cells having differential outputs which are provided to supply a combined differential output current.

6. The MOS four-quadrant multiplier according to claim 5, wherein a drain of each transistor of the second pair of transistors of one of said first and second variable-gain cells is connected in common to respective drains of the second and third pairs of transistors in each of said first and second variable-gain cells.

7. The MOS four-quadrant multiplier according to claim 5, wherein a drain of each transistor of said second pair of transistors of one of said first and second variable-gain cells is directly connected in common to a respective drain of one of the transistors of said second pair of transistors in the other of said first and second variable-gain cells.

8. The MOS four-quadrant multiplier according to claim 5, wherein a power supply voltage is applied to the drains of the third pair of transistors in each of said first and second variable-gain cells.

9. The MOS four-quadrant multiplier according to claim 5, wherein the gates of the first pair of transistors are connected in common to each other and said first differential input voltage is applied between the gates of the first pair of transistors in said first and second variable-gain cells.

10. The MOS four-quadrant multiplier according to claim 5, wherein said first differential input voltage is applied between the gates of the first pair of transistors.