Fully synchronous pipelined RAM

  • US 5,828,606 A
  • Filed: 05/28/1997
  • Issued: 10/27/1998
  • Est. Priority Date: 04/19/1996
  • Status: Expired due to Term
First Claim
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1. A structure which comprises:

  • a memory;

    an input circuit coupled to receive a memory address, a read/write control signal and write data to be written into the memory, said input circuit including one or more storage registers for storing the write data to be written into the memory prior to writing the write data into the memory, the storage registers being capable of receiving and storing the write data on a rising edge of a clock signal; and

    a logic circuit for causing the stored write data to be written from the input circuit into the memory during a pth write operation following the write operation during which said write data was placed in said storage registers, while causing the write data to be held in the storage registers during any intervening read and write operations, where p is a selected integer.

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