Output circuit for use in a semiconductor integrated circuit

• US 5,831,449 A
• Filed: 04/21/1997
• Issued: 11/03/1998
• Est. Priority Date: 02/16/1994
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shigehara, Hiroshi, Kinugasa, Masanori
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/844,663
• Time in Patent Office: 561 Days
• Field of Search: 326/21, 326/27, 326/80-81, 326/83, 326/86, 326/121, 326/68, 326/57-58, 327/534, 327/537
• US Class Current: 326/81
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state

Abstract

An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.

Claims

1. An output circuit comprising:

a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential;

a first switch coupled between said back gate and said gate of said first MOS transistor, said first switch being ON/OFF controlled by a control signal;

a first node supplied with a first potential;

a second node supplied with a second potential lower than the first potential;

a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential applying circuit including a first end coupled to said second node and a second end;

a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled based on an enable signal and a potential at one of said source and said drain of said first MOS transistor;

a third node supplied with a first reference potential; and

a third switch connected between said back gate of said first MOS transistor and said third node,

wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch, thereby to operate said first MOS transistor in a sub-threshold region.

2. The output circuit according to claim 1, wherein a first circuit is coupled between said first node and said second switch.

3. The output circuit according to claim 1, wherein said first and second switches are controlled such that said potential-applying circuit changes said potential difference between said source and said gate of said first MOS transistor to substantially zero and then drives said first MOS transistor in the sub-threshold region.

4. The output circuit according to claim 1, further comprising a second MOS transistor of the same conductivity type as said first MOS transistor, said second MOS transistor having a source coupled to one end of said third switch and a drain and a gate both coupled to said back gate of said first MOS transistor.

5. The output circuit according to claim 4, wherein said second MOS transistor has a threshold voltage which is equal to or less than a threshold voltage of said first MOS transistor in terms of absolute value.

6. The output circuit according to claim 1, further comprising a second MOS transistor of the same conductivity type as said first MOS transistor, said second MOS transistor having a source coupled to one end of said third switch, a drain coupled to said back gate of said first MOS transistor and a gate coupled to said gate of said first MOS transistor.

7. The output circuit according to claim 6, wherein said second MOS transistor has a threshold voltage which is equal to or less than a threshold voltage of said first MOS transistor in terms of absolute value.

8. The output circuit according to claim 1, wherein the control signal is a signal having a level which varies in accordance with an operational state of said output circuit.

9. The output circuit according to claim 1, wherein said first switch comprises a second MOS transistor having a source/drain terminal coupled to said back gate of said first MOS transistor, a drain/source terminal coupled to said gate of said first MOS transistor, and a gate electrode supplied with the control signal.

10. The output circuit according to claim 1, further comprising:

an output terminal, wherein said one of said source and said drain of said first MOS transistor is coupled to said output terminal.

11. The output circuit according to claim 1, wherein said second switch is switched ON when the enable signal enables said output circuit and said second switch is switched ON and OFF in accordance with the potential at said one of said source and said drain of said first MOS transistor when the enable signal disables said output circuit.

12. An output circuit comprising:

a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential;

a first switch coupled between said back gate and said gate of said first MOS transistor;

a first node supplied with a first potential;

a second node supplied with a second potential lower than the first potential;

a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit including a first end coupled to said second node and a second end;

a second switch coupled between said first node and said second end of said potential applying circuit, said second switch being ON/OFF controlled based on an enable signal and a potential at one of said source and said drain of said first MOS transistor; and

a third switch coupled between said back gate and said source of said first MOS transistor,

wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch, thereby to operate said first MOS transistor in a sub-threshold region.

13. The output circuit according to claim 12, wherein said first switch is ON/OFF controlled by a signal having a level which varies in accordance with an operational state of said output circuit.

14. The output circuit according to claim 12, wherein said first switch comprises a second MOS transistor having a source/drain terminal coupled to said back gate of said first MOS transistor, a drain/source terminal coupled to said gate of said first MOS transistor, and a gate electrode supplied with the control signal.

15. The output circuit according to claim 12, further comprising:

an output terminal, wherein said one of said source and said drain of said first MOS transistor is coupled to said output terminal.

16. The output circuit according to claim 12, wherein said second switch is switched ON when the enable signal enables said output circuit and said second switch is switched ON and OFF in accordance with the potential at said one of said source and said drain of said first MOS transistor when the enable signal disables said output circuit.

17. An output circuit comprising:

a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential;

a first switch coupled between said back gate and said gate of said first MOS transistor;

a first node supplied with a first potential;

a second node supplied with a second potential lower than the first potential;

a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit including a first end coupled to said second node and a second end; and

a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled based on an enable signal and a potential at one of said source and said drain of said first MOS transistor,

wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch, thereby to operate said first MOS transistor in a sub-threshold region.

18. The output circuit according to claim 17, wherein said first switch is ON/OFF controlled by a signal having a level which varies in accordance with an operational state of said output circuit.

19. The output circuit according to claim 17, wherein said first switch comprises a second MOS transistor having a source/drain terminal coupled to said back gate of said first MOS transistor, a drain/source terminal coupled to said gate of said first MOS transistor, and a gate electrode supplied with the control signal.

20. The output circuit according to claim 17, further comprising:

an output terminal, wherein said one of said source and said drain of said first MOS transistor is coupled to said output terminal.

21. The output circuit according to claim 17, wherein said second switch is switched ON when the enable signal enables said output circuit and said second switch is switched ON and OFF in accordance with the potential at said one of said source and said drain of said first MOS transistor when the enable signal disables said output circuit.

22. An output circuit comprising:

a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential;

a first node supplied with a first potential;

a second node supplied with a second potential lower than the first potential;

a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit having a node from which to apply the potential and including a first end coupled to said second node and a second end;

a first switch coupled between said back gate of said first MOS transistor and said node of said potential-applying circuit;

a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled by an enable signal;

a third node supplied with a first reference potential; and

a third switch coupled between said back gate of said first MOS transistor and said third node,

wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch and through said potential-applying circuit, thereby to operate said first MOS transistor in a sub-threshold region.

23. The output circuit according to claim 22, wherein said first switch is ON/OFF controlled by a signal having a level which varies in accordance with an operational state of said output circuit.

24. The output circuit according to claim 22, wherein said second switch is ON/OFF controlled by the enable signal and a potential at one of said source and said drain of said first MOS transistor.

25. An output circuit comprising:

a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential;

a first node supplied with a first potential;

a second node supplied with a second potential lower than the first potential;

a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit having a node from which to apply the potential and including a first end coupled to said second n ode and a second end;

a first switch coupled between said back gate of said first MOS transistor and said node of said potential-applying circuit;

a second switch connected between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled by an enable signal; and

a third switch connected between said back gate and said source of said first MOS transistor,

wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch and through said potential-applying circuit, thereby to operate said first MOS transistor in a sub-threshold region.

26. The output circuit according to claim 25, wherein said first switch is ON/OFF controlled by a signal having a level which varies in accordance with an operations state of said output circuit.

27. The output circuit according to claim 25, wherein said second switch is ON/OFF controlled by the enable signal and a potential at one of said source and said drain of said first MOS transistor.

28. An output circuit comprising:

a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential;

a first node supplied with a first potential;

a second node supplied with a second potential lower than the first potential;

a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit having a node from which to apply the potential and including a first end coupled to said second node and a second end;

a first switch coupled between said back gate of said first MOS transistor and said node of said potential-applying circuit; and

a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled by an enable signal,

wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch and through said potential-applying circuit, thereby to operate said first MOS transistor in a sub-threshold region.

29. The output circuit according to claim 28, wherein said first switch is ON/OFF controlled by a signal having a level which varies in accordance with an operational state of said output circuit.

30. The output circuit according to claim 28, wherein said second switch is ON/OFF controlled by the enable signal and a potential at one of said source and said drain of said first MOS transistor.

31. An output circuit comprising:

a first node supplied with a high potential;

a second node supplied with a low potential;

an output terminal;

a first MOS transistor having a source coupled to said first node, a drain coupled to said output terminal, a gate, and a back gate isolated from said source in terms of potential;

a potential-applying circuit for applying a potential;

a first path gate coupled between said back gate and said gate of said first MOS transistor;

a second path gate coupled between an output node of said potential-applying circuit and said gate of said first MOS transistor;

a third path gate coupled between said output node of said potential-applying circuit and said gate of said first MOS transistor; and

a control circuit supplied with the high potential and the low potential and a potential of said output terminal, for applying the potential of said output terminal or the low potential, which is required to render said second path gate conducting, to said second path gate in accordance with a control signal, for applying a potential, which is required to control the ON/OFF state of said first path gate, to said first path gate in accordance with the control signal, and for applying a potential, which is required to control the ON/OFF state of said third path gate, to said third path gate in accordance with the control signal,

wherein a voltage is generated at said back gate of said first MOS transistor so that said back gate and said source of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate, and is applied from said back gate to said gate of said first MOS transistor through said first path gate, thereby to operate said first MOS transistor in a sub-threshold region.

32. An output circuit comprising:

a first node supplied with a high potential;

a second node supplied with a low potential;

an output terminal;

a PMOS transistor having a source coupled to said first node, a drain coupled to said output terminal, a gate, and a back gate isolated from said source in terms of potential;

a potential-applying circuit for applying a potential;

a first path gate coupled between said back gate and said gate of said PMOS transistor;

a second path gate coupled between an output node of said potential-applying circuit and said gate of said PMOS transistor;

a third path gate coupled between said output node of said potential-applying circuit and said gate of said PMOS transistor; and

a control circuit supplied with the high potential and the low potential and a potential of said output terminal, for applying the potential of said output terminal or the low potential, which is required to render said second path gate conducting, to said second path gate in accordance with a control signal, for applying a potential, which is required to control the ON/OFF state of said first path gate, to said first path gate in accordance with the control signal, and for applying a potential, which is required to control the ON/OFF state of said third path gate, to said third path gate in accordance with the control signal,

wherein a voltage is generated at said back gate of said PMOS transistor so that said back gate and said source of said PMOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate, and is applied from said back gate to said gate of said PMOS transistor through said first path gate, thereby to operate said PMOS transistor in a sub-threshold region.

33. The output circuit according to claim 32, further comprising a fourth path gate connected between said first node and said back gate of said PMOS transistor, said fourth path gate being ON/OFF controlled by the control signal of said control circuit.

34. The output circuit according to claim 32, wherein said first and second path gates are PMOS transistors and said third path gate is NMOS transistor.

35. The output circuit according to claim 32, further comprising an NMOS transistor having a source connected to said second node, a drain connected to said output terminal, and a gate.

36. An output circuit comprising:

a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential;

a first switch having a first terminal coupled to said back gate of first MOS transistor, a second terminal coupled to said gate of said first MOS transistor, and a control terminal supplied with a control signal for controlling the ON/OFF switching of said first switch;

a first node supplied with a first potential;

a second node supplied with a second potential lower than the first potential;

a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit including a first end coupled to said second node and a second end; and

a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled based on an enable signal and a potential at one of said source and said drain of said first MOS transistor.