Interconnect scheme for integrated circuits

• US 5,834,845 A
• Filed: 09/21/1995
• Issued: 11/10/1998
• Est. Priority Date: 09/21/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Stolmeijer, Andre
• Primary Examiner(s): BROWN, PETER T
• Application Number:
  US08/532,915
• Time in Patent Office: 1,146 Days
• Field of Search: 257/752, 257/758-760, 257/751, 257/763, 257/764, 257/765
• US Class Current: 257/752
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A novel interconnect layout method and metallization scheme is provided that simplifies the process of fabricating multilayer interconnects. The process of the present invention provides a multilevel interconnect structure formed solely from patterned metal layers stacked on top of each other. Both interconnect lines which form electrical connections along horizontal paths, as well as contacts which form electrical connections along vertical paths, can be formed using patterned metal interconnects as building-blocks. No specific process module is needed for contact layers. The use of patterned metal layers formed from the same process modules makes both design and construction of multilayer interconnects simpler. Accordingly, the manufacturing process is simplified, thus resulting in lower cost. To form thicker metal layers for the purpose of constructing thick interconnect lines, two or more patterned metal layers may be stacked on each other. In this manner, vertical low ohmic bussing is made possible.

Claims

1. A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein which are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure further comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said conductor layer and a substantially thinner barrier layer, said single conductor layer comprising metal selected from the group consisting of aluminum, aluminum alloy, tungsten, and copper, said single conductor layer in some of said plurality of planar structures comprising tungsten and said single conductor layer in others of said plurality of planar structures comprising aluminum, said patterned metal layer having a thickness, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dielectric regions, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connections along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein each said planar structure simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connections along paths parallel to said semiconductor substrate and wherein said thickness across each of said patterned metal layers in each of said planar structures is essentially the same.

2. The multilayer interconnect structure of claim 1 wherein said plurality of planar structures are formed on an initial patterned metal layer contacting at least one of said conducting regions in said semiconductor substrate, said initial patterned metal layer embedded in said insulating regions plus an initial layer of said dielectric, at least one of said metal regions in said plurality of planar structures forming electrical contact with said initial patterned metal layer.

3. The multilayer interconnect structure of claim 1 wherein said substantially thinner barrier layer comprises a refractory metal.

4. The multilayer interconnect structure of claim 1 wherein the cross-section of each of said metal regions has a ratio of height to width not greater than 2.

5. The multilayer interconnect structure of claim 1 wherein said dielectric is selected from the group consisting of oxides, nitrides, and oxy-nitrides.

6. The multilayer interconnect structure of claim 5 wherein said dielectric is selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, aluminum oxide, and boron nitride.

7. The multilayer interconnect structure of claim 1 further comprising an etch stop layer beneath at least one of said layers of said dielectric.

8. A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein which are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure further comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said conductor layer and a substantially thinner barrier layer, said single conductor layer comprising metal selected from the group consisting of aluminum, aluminum alloy, tungsten, and copper, said single conductor layer in some of said plurality of planar structures comprising tungsten and said single conductor layer in others of said plurality of planar structures comprising aluminum, said patterned metal layer having a thickness, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dielectric regions, said dielectric layer formed on top of an etch stop layer, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connections along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein each said planar structure simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connections along paths parallel to said semiconductor substrate and wherein said thickness across each of said patterned metal layers in each of said planar structures is essentially the same.

9. The multilayer interconnect structure of claim 8 wherein said plurality of planar structures are formed on an initial patterned metal layer contacting at least one of said conducting regions in said semiconductor substrate, said initial patterned metal layer embedded in said insulating regions plus an initial layer of said dielectric, at least one of said metal regions in said plurality of planar structures forming electrical contact with said initial patterned metal layer.

10. The multilayer interconnect structure of claim 8 wherein said substantially thinner barrier layer comprises a refractory metal.

11. The multilayer interconnect structure of claim 8 wherein each said planar structures simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connection along paths parallel to said semiconductor substrate.

12. The multilayer interconnect structure of claim 8 wherein the cross-section of each of said metal regions has a ratio of height to width not greater than about 2.

13. The multilayer interconnect structure of claim 8 wherein said dielectric is selected from the group consisting of oxides, nitrides, and oxy-nitrides.

14. The multilayer interconnect structure of claim 13 wherein said dielectric is selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, aluminum oxide, and boron nitride.

15. A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein which are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said single conductor layer and a substantially thinner barrier layer, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dielectric regions, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connection along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein some of said single conductor layers comprise tungsten and other of said single conductor layers comprise aluminum.

16. The multilayer interconnect structure of claim 15 wherein said plurality of planar structures are formed on an initial patterned metal layer contacting at least one of said conducting regions in said semiconductor substrate, said initial patterned metal layer embedded in said insulating regions plus an initial layer of said dielectric, at least one of said metal regions in said plurality of planar structures forming electrical contact with said initial patterned metal layer.

17. The multilayer interconnect structure of claim 15 wherein said substantially thinner barrier layer comprises a refractory metal.

18. The multilayer interconnect structure of claim 15 wherein each said planar structure simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connection along paths parallel to said semiconductor substrate.

19. The multilayer interconnect structure of claim 15 wherein the cross-section of each of said metal regions has a ratio of height to width not greater than 2.

20. The multilayer interconnect structure of claim 15 wherein the thickness of each of said patterned metal layers in each of said planar structures is essentially the same.

21. The multilayer interconnect structure of claim 15 wherein said single conductor layer comprises metal selected from the group consisting essentially of aluminum, aluminum alloy, tungsten, and copper.

22. The multilayer interconnect structure of claim 15 wherein said dielectric is selected from the group consisting of oxides, nitrides, and oxy-nitrides.

23. The multilayer interconnect structure of claim 22 wherein said dielectric is selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, aluminum oxide, and boron nitride.

24. The multilayer interconnect structure of claim 15 further comprising an etch stop layer beneath at least one of said layers of said dielectric.

25. A multilayer interconnect structure for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said semiconductor substrate containing conducting regions therein that are electrically contacted by portions of said multilayer interconnect structure, said multilayer interconnect structure comprising a plurality of planar structures stacked one on top of another over said semiconductor substrate, each planar structure having a top surface and a bottom surface and having at least one adjacent planar structure contacting said top surface, said bottom surface, or both, and each planar structure comprising a patterned metal layer comprising either a single conductor layer or said single conductor layer and a substantially thinner barrier layer, said patterned metal layer embedded in a dielectric, thereby forming metal regions and dill electric regions, said dielectric formed on top of an etch stop layer, said patterned metal layer exposed at both said top surface and said bottom surface of said planar structures, thereby enabling electrical contact to be formed between selected metal regions in said adjacent planar structures so as to form electrical connection along paths perpendicular to said semiconductor substrate and electrical connection on paths parallel to said semiconductor substrate, wherein some of said single conductor layers comprise tungsten and other of said single conductor layers comprise aluminum.

26. The multilayer interconnect structure of claim 25 wherein said plurality of planar structures are formed on an initial patterned metal layer contacting at least one of said conducting regions in said semiconductor substrate, said initial patterned metal layer embedded in said insulating regions plus an initial layer of said dielectric, at least one of said metal regions in said plurality of planar structures forming electrical contact with said initial patterned metal layer.

27. The multilayer interconnect structure of claim 25 wherein said substantially thinner barrier layer comprises a refractory metal.

28. The multilayer interconnect structure of claim 25 wherein each of said planar structures simultaneously forms electrical connection along paths perpendicular to said semiconductor substrate and electrical connection along paths parallel to said semiconductor substrate.

29. The multilayer interconnect structure of claim 25 wherein the cross-section of each of said metal regions has a ratio of height to width not greater than 2.

30. The multilayer interconnect structure of claim 25 wherein the thickness of each of said patterned metal layers in each of said planar structures is essentially the same.

31. The multilayer interconnect structure of claim 25 wherein said single conductor layer comprises metal selected from the group consisting essentially of aluminum, aluminum alloy, tungsten, and copper.

32. The multilayer interconnect structure of claim 25 wherein said dielectric is selected from the group consisting of oxides, nitrides, and oxy-nitrides.

33. The multilayer interconnect structure of claim 32 wherein said dielectric is selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, aluminum oxide, and boron nitride.