Bus-to-bus bridge in computer system, with fast burst memory range

• US 5,835,741 A
• Filed: 12/31/1996
• Issued: 11/10/1998
• Est. Priority Date: 12/31/1996
• Status: Expired

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Hausauer, Brian S., Riley, Dwight, Pettey, Christopher J., Seeman, Thomas R., Elkhoury, Bassam
• Primary Examiner(s): Auve, Glenn A.
• Application Number:
  US08/777,597
• Time in Patent Office: 679 Days
• Field of Search: 395/287, 395/308, 395/309, 395/855, 711/146
• US Class Current: 710/310
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches a bridge interface from the PCI bus, and it is recognized that the address is within the fast burst range, then the fast burst mode is allowed, and write or read requests can be issued without waiting for the snoop phase, since there is no possibility of defer or retry.

Claims

1. A method of operating a computer system of the type having a CPU with a system bus coupled to the CPU, a main memory coupled to said system bus, and having an expansion bus coupled to the system bus by a bridge, comprising the steps of:

initiating by said CPU a transaction on said system bus directed to a device coupled to said expansion bus, said transaction being initiated by a request being applied to said system bus by said CPU, followed by a snoop phase and a response phase

initiating first and second transactions on said system bus directed to said main memory, said transactions being initiated by a first request being applied to said system bus, followed immediately by a second request, without waiting for a snoop phase.

2. A method according to claim 1 wherein said expansion bus is a standardized "PCI" bus.

3. A method according to claim 2 wherein said CPU is a microprocessor of the "Pentium Pro" type.

4. A method according to claim 1 including the step of designating a range of memory as a fast burst memory region and initiating a pair of transactions consecutively, without waiting for a snoop phase, when said first transaction is addressed to said range.

5. A method according to claim 4 wherein said fast burst memory region includes the range of addresses of said main memory.

6. A method according to claim 1 wherein said CPU initiated transactions may include a retry or deferred response and said first transaction may not include a retry or deferred response.

7. A computer system, comprising:

a CPU;

a system bus coupled to the CPU;

a main memory coupled to said system bus;

an expansion bus coupled to the system bus by a bridge;

a signal path element of said system bus for initiating by said CPU a transaction on said system bus directed to a device coupled to said expansion bus, said transaction being initiated by a request being applied to said system bus by said CPU, followed by a snoop phase;

said signal path element also providing for initiating first and second transactions on said system bus directed to said main memory, said first transaction being initiated by a first request being applied to said system bus, followed immediately by a second request, without waiting for a snoop phase.

8. A system according to claim 7 wherein a fast burst memory range is defined by information stored in said bridge and said path element adapted to begin said second transaction without waiting for said snoop phase of said first transaction when said first transaction is directed to said range.

9. A system according to claim 8 wherein said first and second transactions are initiated by said bridge.

10. A system according to claim 7 wherein said expansion bus is a standardized "PCI" bus.

11. A system according to claim 10 wherein said CPU is a microprocessor of the "Pentium Pro" type.