Chip carrier to allow electron beam probing and FIB modifications

• US 5,838,159 A
• Filed: 03/22/1996
• Issued: 11/17/1998
• Est. Priority Date: 03/22/1996
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Johnson, Douglas S.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US08/620,274
• Time in Patent Office: 970 Days
• Field of Search: 324/755, 324/500, 324/501, 324/750, 324/751, 324/752, 324/754, 365/200
• US Class Current: 324/754.08
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: G01R 31/307 of integrated circuits

Abstract

Disclosed are a die carrier and associated method for conducting probe beam tests on chips designed to be packaged in flip-chip packages. The die carrier is a specially modified membrane type carrier that includes a probe access region, such as an opening, in the membrane. A die to be tested is mounted in the die carrier such that its I/O pads make electrical contact with corresponding bump contacts on the membrane. The die/carrier assembly is then mounted in a test socket provided on a chip testing apparatus such that electrical I/O signals can be provided to and from an external test circuit. While the die is being electrical tested, a probe beam is directed through the probe access region and onto the chip active surface. In this manner, the chip active surface is probed while exposed to electrical stimulus.

Claims

1. A method for probing an active region of a die including one or more peripheral input/output bump pads located about the periphery of the active region of said die, the method comprising the steps of:

supporting said die in a die carrier such that said peripheral bump pads are electrically connected to an external test circuit; and

accessing the active region with a probe beam directed onto the active region of the die through a probe access region,

wherein the die carrier includes

(a) a membrane having (i) said probe access region for allowing the probe beam to access substantially all of the die'"'"'s active region, (ii) a plurality of peripheral bump contacts adjacent to the probe access region and arranged to make electrical contact with said peripheral bump pads of the die, and (iii) a plurality of socket contacts electrically connected to said peripheral bump contacts; and

(b) a membrane carrier supporting said membrane and having an opening corresponding, at least in part, to the location of said probe access region of the membrane.

2. The method of claim 1 wherein the probe beam is an electron beam.

3. The method of claim 1 wherein the probe beam is a focused ion beam.

4. The method of claim 3 further comprising a step of modifying a circuit with said focused ion beam.

5. The method of claim 1 wherein the active region of said die includes one or more area input/output bump pads located within the periphery of said die, and wherein the step of supporting the die in the die carrier causes said area bump pads to make electrical contact with an area bump contact section spanning said probe access region of said membrane and including one or more area bump contacts arranged to line up with the area bump pads on said die.

6. The method of claim 1 wherein the active region of said die includes one or more area input/output bump pads located within the periphery of said die, and further comprising a step of electrically contacting one or more of said area bump pads with an external mechanical probe protruding through said probe access region.

7. The method of claim 1 further comprising a step of mounting said die carrier in a test socket of a test apparatus, whereby the socket contacts make electrical contact with corresponding contacts on the test socket.

8. The method of claim 1 wherein the die is designed for use in a flip-chip package.