Fully synchronous pipelined ram

• US 5,841,732 A
• Filed: 05/28/1997
• Issued: 11/24/1998
• Est. Priority Date: 04/19/1996
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Mick, John R.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/864,285
• Time in Patent Office: 545 Days
• Field of Search: 365/230.01, 365/230.06, 365/233.5, 365/230.02
• US Class Current: 365/233.1
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no "bus turnaround" down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Claims

1. The method of writing data into memory and reading data from a memory system which includes said memory which comprises:

placing write data to be stored in said memory and the address at which said write data is to be stored into storage registers external to said memory,

storing said write data in said storage registers during the execution of one or more read cycles, reading said write data stored in said storage registers out of the memory system should the address of the data to be read from the memory system correspond to the address of the write data stored in said storage registers and reading the data out of said memory should the address of the data to be read from the memory system not correspond to the address of the write data stored in said storage registers; and

writing the write data stored in said storage registers into said memory on a subsequent write cycle.

2. The method of claim 1 wherein the write data to be written into said memory appears on a Data I/O bus to said memory system p cycles after the address and write control signals are placed on the address input bus and control input bus, respectively, to said memory system, where p is a selected integer given by 1≦

p≦

P.

3. The method as in claim 2 wherein said write data to be written into said memory system appears on a Data I/O bus to said memory system two clock cycles after the address and the write control signals appear on the address bus and the control bus to said memory system.

4. The method as in claim 2 wherein said write data to be written into said memory system appears on a Data I/O bus to said memory system one clock cycle after the address and the write control signals appear on the address bus and the control bus to said memory system.

5. The method of claim 2 wherein said write data to be written into said memory is stored in a storage register outside said memory when one or more read commands are received in sequence immediately following said write operation and said write data is written into said memory on the next write operation following the write operation during which the write data was placed on the Data I/O bus of the memory system.

6. The method of claim 3 wherein said memory system is capable of holding up to two sets of write data in storage registers outside said memory for the duration of a sequence of one or more read operations following said two write operations, said system then allowing the oldest write data to be written into said memory upon receipt of the next following write control signal.

7. The method of claim 5 wherein the operation of said system is such that the Data I/O bus of the system, for each cycle of operation, carries either write data to be written into the memory or data read out from the memory, thereby to increase the bandwidth of the memory system.

8. The method of claim 6 wherein the operation of said system is such that the Data I/O bus of the system for each cycle of operation, carries either write data to be written into the memory or data read out from the memory, thereby to increase the bandwidth of the memory system.