Padding apparatus for passing an arbitrary number of bits through a buffer in a pipeline system

• US 5,842,033 A
• Filed: 03/07/1995
• Issued: 11/24/1998
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Sotheran, Martin, Wise, Adrian P., Robbins, William P.
• Primary Examiner(s): Pan, Daniel H.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/400,211
• Time in Patent Office: 1,358 Days
• Field of Search: 395/800, 395/375, 395/377
• US Class Current: 712/1
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. In a pipeline system, the improvement comprising:

a fixed size, fixed width buffer; and

means for padding said buffer to pass an arbitrary number bits through said buffer, wherein said bits comprise a stream of tokens, and a said comprises a plurality of data words, each said word including an extension indicator which indicates a presence or an absence of additional words in said token, a length of said token being determined by said extension indicators, whereby the length of said token can be unlimited;

wherein said means for padding is pipelined with another member of said pipeline system by a two-wire link defining a sender, and a receiver, and further comprises a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready, wherein said two-wire link further comprises;

electrical validation circuitry in at least one of said sender and said receiver to generate a validation signal for a first state when data stored in said stage is valid and for a second state when data stored in said stage is invalid, said validation circuitry including at least one storage device to store said validation signal;

an acceptance signal connected between said sender and said receiver conveying an acceptance signal indicative of the ability of said receiver to load data stored in the sender; and

enabling circuitry connected to said storage devices for generating an enabling signal to enable loading of data and validation signals into said storage device;

wherein;

said storage device includes a primary data storage device and a secondary data storage device;

said data is loaded into said respective primary data storage devices and said validation signal is loaded into a respective secondary validation storage device at the same time;

data is loaded into said respective primary data storage device when said acceptance signal assumes an enabling state; and

said acceptance signal assumes said enabling state only when the acceptance signal associated with the data storage device of said receiver is in said enabling state or said data in said data storage device of said receiver is invalid.

2. A system as recited in claim 1, wherein said means for padding is a start code detector.

3. A system as recited in either claim 1 or 2, wherein said padding is performed only on the last word of a token.

4. A system as recited in claim 1, and further comprising:

a reconfigurable processing stage as a spatial decoder; and

said means for padding adds to picture data being handled by said spatial decoder sufficient additional bits such that each decompressed picture at the output of said spatial decoder is of the same length in bits.

5. A system as recited in either claim 1 or 2, wherein said extension indicator is an extension bit.