Method for automatic iterative area placement of module cells in an integrated circuit layout
First Claim
1. A computer-implemented automation tool for automatic area placement in designing circuit layouts for semiconductor integrated circuits, comprising:
- a computer platform for processing a plurality of program execution modules which accept a set of placement options and initial conditions related to a semiconductor integrated circuit design, computes an area placement solution, and that outputs a completed layout that is used as a guide for the fabrication of a semiconductor integrated circuit;
a first computer process for searching in an area-placement-solution computation for a hot-spot candidate with a relatively high concentration of overlapping connections for further refining, and for loading and execution on the computer platform as one of said program execution modules;
a second computer process for refining said hot-spot candidate by matching it with an area box having a particular combination of aspect ratio, cut-line direction, and placement options, and for loading and execution on the computer platform as one of said program execution modules; and
a third computer process connected to receive a plurality of refined ones of said hot-spot candidates, for scheduling area-placement-solution-computation repetitions, and for loading and execution on the computer platform as one of said program execution modules.
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Abstract
In a computer system, a method for an area based place and route of an integrated circuit layout that provides automatic iterative area placement of module cells intelligently and effectively. In one embodiment, this is accomplished in three phases. The searching phase determines which hot spot is to be refined based on a congestion map. Next, the refining phase chooses a box with the proper aspect ratio, cut line direction, and placement options for minimizing the hot spot. The scheduling phase then decides whether to proceed with another area placement based on the current result or to restore a previous placement that exhibited superior characteristics. In the course of the area placements, several parameters are randomly varied in an intelligent manner so that successive iterative area placements produce equivalent or better results. All of this is accomplished without human intervention or expert knowledge. Instead, the computer system continuously runs its program until a design goal is attained.
99 Citations
8 Claims
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1. A computer-implemented automation tool for automatic area placement in designing circuit layouts for semiconductor integrated circuits, comprising:
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a computer platform for processing a plurality of program execution modules which accept a set of placement options and initial conditions related to a semiconductor integrated circuit design, computes an area placement solution, and that outputs a completed layout that is used as a guide for the fabrication of a semiconductor integrated circuit; a first computer process for searching in an area-placement-solution computation for a hot-spot candidate with a relatively high concentration of overlapping connections for further refining, and for loading and execution on the computer platform as one of said program execution modules; a second computer process for refining said hot-spot candidate by matching it with an area box having a particular combination of aspect ratio, cut-line direction, and placement options, and for loading and execution on the computer platform as one of said program execution modules; and a third computer process connected to receive a plurality of refined ones of said hot-spot candidates, for scheduling area-placement-solution-computation repetitions, and for loading and execution on the computer platform as one of said program execution modules.
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2. A computer-implemented automation tool for automatic area placement in designing circuit layouts for semiconductor integrated circuits, comprising:
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a placement engine that calls for horizontal cuts to reduce vertical congestion and vertical cuts to reduce horizontal congestion, and providing for a generating of a plurality of placement congestion maps for a circuit layout for a semiconductor integrated circuit, wherein each of said placement congestion maps is a two-dimensional routing display for a particular placement and contains both vertical and horizontal routing congestion information; a search mechanism providing for an identification within said plurality of placement congestion maps of a target hot-spot candidate with a relatively high concentration of overlapping connections; a refining mechanism providing for a refined target hot-spot from said identified target hot-spot candidate and a surrounding adjacent area; and a scheduling mechanism providing for a decision whether to proceed with a placement solution that includes said refined target hot-spot candidate and then repeat, or to restore a previous placement solution and then repeat, and wherein said decision is based on at least one of a count of a number of iterations, a run-time limit, and an attained placement goal. - View Dependent Claims (3, 4, 5, 6, 7)
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8. A computer-implemented method for automatic area placement in designing circuit layouts for semiconductor integrated circuits, comprising the steps of:
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computer processing a plurality of program execution modules which accept a set of placement options and initial conditions related to a semiconductor integrated circuit design, and that then compute an area placement solution, and output a completed layout for use as a fabrication guide for a semiconductor integrated circuit; using one of one of said program execution modules to search in an area-placement-solution computation for a hot-spot candidate with a relatively high concentration of overlapping connections for further refining; using one of one of said program execution modules to refine said hot-spot candidate by matching it with an area box having a particular combination of aspect ratio, cut-line direction, and placement options; and using one of one of said program execution modules to receive a plurality of refined ones of said hot-spot candidates and schedule area-placement-solution-computation repetitions.
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Specification