Trench-gated vertical CMOS device

• US 5,864,158 A
• Filed: 04/04/1997
• Issued: 01/26/1999
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Liu, Yowjuang W., Wollesen, Donald L.
• Primary Examiner(s): WALLACE, VALENCIA MARTIN
• Application Number:
  US08/832,657
• Time in Patent Office: 662 Days
• Field of Search: 257/329, 257/330, 257/347, 257/351, 257/369, 257/374, 257/466
• US Class Current: 257/330
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).

Claims

1. A vertical insulated-gate field-effect transistor, comprising:

a substrate;

a semiconductor layer formed on said substrate to be of a first conductivity type and having a surface;

a heavily doped region formed in said semiconductor layer to be spaced from said surface of said semiconductor layer and to be of a second conductivity type opposite said first conductivity type, said heavily doped region having a boundary, a channel region of said semiconductor layer disposed adjacent to said boundary of said heavily doped region;

a drain region formed adjacent said surface of said semiconductor layer to be spaced from said heavily doped region by said channel region and to be of said second conductivity type;

an endless sidewall of said channel region extending from said surface of said semiconductor layer to at least said boundary of said heavily doped region;

a gate insulator formed to adjoin said sidewall;

a conductive gate formed adjacent said sidewall so as to laterally surround said channel region; and

means for impressing a source voltage on said heavily doped region.

2. The transistor of claim 1, wherein said means for impressing said source voltage on said heavily doped region is a source contact region formed in said semiconductor layer to be of said second conductivity type, said source contact region spaced from said channel region.

3. The transistor of claim 2, wherein said source contact region is formed to be insulatively adjacent said gate.

4. The transistor of claim 1, wherein said substrate is an insulator.

5. A vertical insulated-gate field-effect transistor, comprising:

a substrate;

a semiconductor layer formed on said substrate to be of a first conductivity type and having a surface spaced from said substrate;

a heavily doped region formed in said semiconductor layer, a boundary of said heavily doped region spaced from said surface of said semiconductor layer, said heavily doped region being of a second conductivity type opposite said first conductivity type;

a channel region defined in said semiconductor layer to have said first conductivity type and being formed adjacent said boundary of said heavily doped region;

a drain region formed adjacent said channel region to be spaced from said boundary of said heavily doped region, to be adjacent said surface of said semiconductor layer and to be of said second conductivity type;

an endless trench formed in said semiconductor layer to extend from said surface of said semiconductor layer to at least said boundary of said heavily doped region and having a sidewall adjacent said channel region; and

a conductive gate formed in said trench to be disposed insulatively adjacent said sidewall and to laterally surround said channel region.

6. The transistor of claim 5, wherein said gate is highly doped polycrystalline silicon.

7. The transistor of claim 5, and further comprising a source connector region extending from said surface of said semiconductor layer to at least said boundary of said heavily doped region, said source connector region being insulatively spaced from said gate and being opposed to said channel region, said source connector region being doped to be of said second conductivity type.

8. The transistor of claim 5, wherein said substrate includes a dielectric layer disposed adjacent to said heavily doped region.

9. The transistor of claim 5, wherein said semiconductor layer is formed as a mesa of semiconductor material.

10. The transistor of claim 9, wherein said mesa has sidewalls, said mesa being laterally isolated by regions of dielectric material disposed adjacent said sidewalls of said mesa.

11. A complementary field effect transistor device, comprising:

a substrate;

a first semiconductor layer formed on a first area of said substrate to be of a first conductivity type and having a top surface;

a first heavily doped region formed in said first semiconductor layer to have an upper boundary spaced from said top surface of said first semiconductor layer and to be of a second conductivity type opposite said first conductivity type, a first channel region of said first semiconductor layer to be of said first conductivity type;

a first drain region formed in said first semiconductor layer adjacent said top surface of said first semiconductor layer and to be spaced from said heavily doped region of said first semiconductor layer by said first channel region, said first drain region formed to be of said second conductivity type;

at least one sidewall of said first channel region extending from said first drain region to at least said upper boundary of said heavily doped region;

a first gate insulator formed on said sidewall;

a first conductive gate formed adjacent said sidewall opposite said first channel region;

a second semiconductor layer formed on a second area of said substrate and having a top surface;

a second heavily doped region formed in said second semiconductor layer to be of said first conductivity type, an upper boundary of said second heavily doped region spaced from said top surface of said second semiconductor layer, a second channel region of said second semiconductor layer having said second conductivity type, the second channel region having a length dimension which is different than a length dimension of the first channel region;

a second drain region formed adjacent said top surface of said second semiconductor layer and to be spaced from said second heavily doped region by said second channel region and to be of said first conductivity type;

at least one sidewall of said second channel region extending from said second drain region to said upper boundary of said second heavily doped region;

a second gate insulator formed on said sidewall of said second channel region;

a second conductive gate formed adjacent said second gate insulator;

means for impressing a drain voltage on said first drain region;

means for impressing a source voltage on said second heavily doped region;

means for conductively coupling together said first heavily doped region with said second drain region; and

means for conductively coupling together said first and second gates.

12. The device of claim 11, wherein said means for impressing a source voltage on said second heavily doped region comprises a source connector region extending from said top surface of said second semiconductor layer to said second heavily doped region;

said source connector region being of said first conductivity type.

13. The device of claim 11, wherein said means for conductively coupling said first heavily doped region with said second drain region comprises a connector region formed in said first semiconductor layer to be of said second conductivity type and to extend from at least said upper boundary of said first heavily doped region to said top surface of said first semiconductor layer.

14. The device of claim 11, wherein said first semiconductor layer is formed in a first mesa, said second semiconductor layer being formed in a second mesa spaced from said first mesa.

15. A vertical insulated-gate field-effect transistor, comprising:

a substrate;

a semiconductor layer formed on said substrate to be of a first conductivity type and having a surface;

a heavily doped region formed in said semiconductor layer to be spaced from said surface of said semiconductor layer and to be of a second conductivity type opposite said first conductivity type, said heavily doped region having a boundary, a channel region of said semiconductor layer disposed adjacent to said boundary of said heavily doped region;

a drain region formed adjacent said surface of said semiconductor layer to be spaced from said heavily doped region by said channel region and to be of said second conductivity type;

at least one sidewall of said channel region extending from said surface of said semiconductor layer to at least said boundary of said heavily doped region;

a gate insulator formed to adjoin said sidewall;

a conductive gate formed adjacent said sidewall opposite said channel region, said drain region being self-aligned to said conductive gate; and

means for impressing a source voltage on said heavily doped region.

16. The transistor of claim 15, wherein said sidewall is endless, said gate laterally surrounding said channel region.

17. The transistor of claim 15, wherein said means for impressing said source voltage on said heavily doped region is a source contact region formed in said semiconductor layer to be of said second conductivity type, said source contact region spaced from said channel region.

18. The transistor of claim 15, wherein said source contact region is formed to be insulatively adjacent said gate.

19. The transistor of claim 15, wherein said substrate is an insulator.