Methods of efficiently recording and reproducing an audio signal in a memory using hierarchical encoding

• US 5,864,801 A
• Filed: 05/15/1998
• Issued: 01/26/1999
• Est. Priority Date: 04/20/1992
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Sugiyama, Kazuhiro, Ishida, Yoshinobu, Ono, Yukari
• Primary Examiner(s): Dorvil, Richemond
• Assistant Examiner(s): Chawan, Vijay B.
• Application Number:
  US09/079,219
• Time in Patent Office: 256 Days
• Field of Search: 704/229, 704/230, 704/203, 704/201, 369/48, 369/59, 369/60, 369/58
• US Class Current: 704/229
• CPC Class Codes: G11C 2207/16 Solid state audio deprecated, only for historical reasons, G06F3/16, G11B
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

An audio signal is recorded in a semiconductor memory in a plurality of hierarchical levels, with the lowest level sufficing for reproduction with a certain reduced degree of fidelity. Successfully higher hierarchical levels provide successively greater fidelity when reproduced. When the memory has been determined to have reached maximum capacity, recording continues by overwriting the highest hierarchical level of data currently stored in the memory with lower hierarchical levels of new data. A code is recorded in the memory, indicating the number of hierarchical levels recorded therein, for subsequent reproduction. The audio signal can furthermore be recorded in variable-length frames and reproduced at high speed by reading every N-th frame, N being a positive integer, or by reading only frames having at least a certain minimum length.

Claims

1. An apparatus for recording a signal in a memory and for reproducing the signal, comprising:

an analog-to-digital converter for converting said signal to first digitized data;

a hierarchical encoder, for encoding said first digitized data to generate a plurality of successive hierarchical levels of data corresponding to the data including a lowest hierarchical level of data for reproduction of the signal with relatively low fidelity, and including at least one other higher hierarchical level of data, each successive higher hierarchical level representing additional data for successively relatively greater fidelity, and for writing said hierarchical levels of data into said memory;

a memory address generator coupled to said hierarchical encoder, for generating memory addresses so that, upon determining that said memory has reached maximum storage capacity, recording can continue by overwriting a highest hierarchical level of data previously recorded in said memory with new data of hierarchical levels lower than the overwritten highest hierarchical level;

a hierarchy code generator coupled to said memory address generator, for recording in said memory, a code indicative of a number of hierarchical levels of data currently recorded therein;

a hierarchy code reader coupled to said memory, for reading said recorded code;

a hierarchical decoder coupled to said memory, for reading a number of hierarchical levels of data designated by said code and for decoding the read data to generate second digitized data; and

a digital-to-analog converter coupled to receive said second digitized data from said hierarchical decoder, for converting said second digitized data to a signal.

2. The apparatus of claim 1, wherein said hierarchical encoder comprises:

a subband analysis filter for filtering said first digitized data and for generating a plurality of subbands of digitized data;

a plurality of transform processors for converting said generated subbands of digitized data into frequency coefficients;

a frequency grouper for dividing said frequency coefficients into groups and for combining the frequency coefficients in each group into a single value;

a bit allocator coupled to said frequency grouper, for allocating a number of bits to each subbands to thereby generate bit allocation information;

a hierarchical quantizer coupled to receive values output from said frequency grouper, for classifying the values into one of a plurality of hierarchical levels; and

a formatter coupled to said hierarchical quantizer and said bit allocator, for recording said classified hierarchical levels of values and said bit allocation information said memory.

3. The apparatus of claim 2, further comprising:

a block size controller coupled to said subband analysis filter, for specifying sizes of data blocks converted by said plurality of transform processors.

4. The apparatus of claim 2, further comprising:

a scale factor generator coupled to said frequency grouper and said formatter, for generating scale factors to enable storage of values output by said hierarchical quantizer without loss of significant digits.

5. The apparatus of claim 1, further comprising:

a clock generator for generating clock signals;

a clock divider coupled to said clock generator, for dividing said clock signals according to a selectable division ratio and for supplying divided clock signals to said digital-to-analog converter;

a speed switch coupled to said clock divider, for selecting said division ratio; and

a hierarchical level selector coupled to said clock divider, for selecting a hierarchical level according to said division ratio and for notifying said hierarchical decoder thereof, thereby causing said hierarchical decoder to decode only hierarchical levels of data which are at most equal to the hierarchical level selected by said hierarchical level selector.

6. The apparatus of claim 5, wherein said hierarchical level selector selects a hierarchical level according to a processing speed of said hierarchical decoder and said division ratio.

7. An apparatus for recording a signal in a memory, comprising:

an analog-to-digital converter for converting said signal to digitized data;

a hierarchical encoder, for encoding said digitized data to generate a plurality of successive hierarchical levels of data corresponding to the signal including a lowest hierarchical level of data for reproduction of the signal with relatively low fidelity, and including at least one other higher hierarchical level of data, each successive higher hierarchical level representing additional data for successively relatively greater fidelity;

a buffer memory coupled to said hierarchical encoder, for storing the hierarchical levels of data generated by said hierarchical encoder;

a memory address generator coupled to said buffer memory, for generating memory addresses at which said hierarchical levels of data are stored;

a data size calculator coupled to said memory address generator, for calculating an amount of data stored in said buffer memory;

a hierarchical level selector coupled to said data size calculator, for determining a number of hierarchical levels of data capable of being stored in said memory, and for copying the number of hierarchical levels of data thus determined from said buffer memory to said memory; and

a hierarchy code generator coupled to said hierarchical level selector, for recording in said memory a code indicative of a number of hierarchical levels of data recorded therein.

8. The apparatus of claim 7, wherein said memory is a removable memory device.

9. The apparatus of claim 7, wherein said hierarchical level selector is adapted to copy data from said buffer memory to said memory at a rate faster than a data storage rate of said buffer memory.

10. The apparatus of claim 7, wherein said buffer memory has sufficient memory capacity to store all of said hierarchical levels of data, even if said memory has capacity to store only said lowest hierarchical level of data.

11. An apparatus for recording data in a memory, comprising:

an encoder for encoding the data by generating a plurality of successive hierarchical levels of data corresponding to the signal including a first hierarchical level of data representing data reproducible at a relatively low fidelity and including at least one other hierarchical level of data higher than the first hierarchical level, each successively higher hierarchical level of data representing data reproducible at a successively relatively greater fidelity; and

a controller for controlling said encoder to record said hierarchical levels of encoded data in the memory and, upon determining that the memory has reached maximum storage capacity, for controlling the encoder to overwrite a highest hierarchical level of previously recorded encoded data in the memory with new encoded data of hierarchical levels lower than the previously recorded highest hierarchical level of encoded data.

12. The apparatus of claim 11, wherein the controller further controls the encoder to record, in the memory, a code indicative of a number of hierarchical levels of data currently recorded therein.

13. The apparatus of claim 12, wherein the encoder encodes input data frame by frame, by generating N hierarchical levels of data for each input frame of data, N being an integer greater than one.

14. The apparatus of claim 12, wherein the code recorded in the memory is updated upon the encoder overwriting each previously recorded highest hierarchical level of data.

15. The apparatus of claim 11, wherein the encoder is controlled to be in one of a write mode for recording encoded data of a successively higher hierarchical level of data into the memory, and an overwrite mode for successively recording, over a highest hierarchical level of data previously recorded in the memory, a first encoded hierarchical level of data and successively higher hierarchical levels of data, each successively higher hierarchical levels being lower than the highest hierarchical levels of data.

16. The apparatus of claim 15, wherein the controller switches the encoder from the write mode to the overwrite mode upon determining that the memory has reached maximum storage capacity.

17. The apparatus of claim 11, wherein the encoder encodes input data cumulatively, such that a frame of input data is encoded by generating N hierarchical levels of data, each successively greater hierarchical level of data cumulatively representing data reproducible at a successively relatively greater fidelity, wherein N is an integer greater than one.