Semiconductor device having an elevated active region formed in an oxide trench and method of manufacture thereof

• US 5,872,038 A
• Filed: 01/08/1997
• Issued: 02/16/1999
• Est. Priority Date: 01/08/1997
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.), Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Gardner, Mark I., Duane, Michael, Kadosh, Daniel
• Primary Examiner(s): Booth, Richard A.
• Application Number:
  US08/780,643
• Time in Patent Office: 769 Days
• Field of Search: 438/279, 438/300, 438/564, 438/692, 438/305
• US Class Current: 438/279
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.

Claims

1. A process of forming a semiconductor device, the process comprising:

forming a plurality of gate electrodes on a substrate, an active region of the substrate being defined by adjacent walls of two gate electrodes;

forming an insulating layer over the gate electrodes and the active region;

etching a trench in the insulating layer to expose a portion of the active region of the substrate;

filling the trench with a polysilicon material; and

doping the polysilicon material to form an elevated active region above the active region of the substrate.

2. A process as recited in claim 1, wherein the insulating layer comprises an oxide layer.

3. A process as recited in claim 1, further comprising implanting a dopant into the active region of the substrate through the trench prior to filling the trench with the polysilicon material.

4. A process as recited in claim 1, wherein the doping of the polysilicon material includes diffusing the dopant through the polysilicon material to dope a region in the active region of the substrate.

5. A process as recited in claim 1, further comprising planarizing the polysilicon material prior to the doping of the polysilicon material.

6. A process as recited in claim 1, further comprising:

forming a nitride layer on the gate electrodes prior to forming the insulating layer; and

chemical mechanical polishing the resultant structure, prior to the doping of the polysilicon material, to planarize the polysilicon material using the nitride layer as a stop layer.

7. A process as recited in claim 6, further comprising:

removing the nitride layer on the gate electrodes;

forming a silicide on a surface of the gate electrodes and on a surface of the elevated active region.

8. A process as recited in claim 1, further comprising:

implanting a first dopant into the active region of the substrate prior to forming the insulating layer to form an LDD region in the active region of the substrate; and

implanting a second dopant using the trench as a pattern to form a source/drain region in the active region of the substrate.

9. A process as recited in claim 1, further comprising forming a silicide layer on a surface of the elevated active region.

12. A process as recited in claim 1, wherein the insulating layer has a thickness of about twice a thickness of the gate electrodes.

13. A process as recited in claim 1, wherein the insulating layer has a thickness greater than a thickness of the gate electrodes.

14. A process as recited in claim 1, wherein etching the trench in the insulating layer leaves portions of the insulating layer between edges of the trench and sidewalls of the gate electrodes.

10. A process of forming a metal-oxide-semiconductor (MOS) device having an elevated source/drain region, the process comprising:

forming a gate oxide layer on a surface of a substrate;

forming a plurality of gate electrodes on a surface of the gate oxide layer to form a resultant structure, adjacent sides of two gate electrodes defining an active region of the substrate for the formation of a source/drain region in the substrate;

forming an oxide layer over the resultant structure;

forming a trench in the oxide layer between the adjacent sides of the two gate electrodes to expose the surface of the substrate over a portion of the active region;

filling the trench with a polysilicon material;

implanting a dopant into the polysilicon material to form the elevated source/drain region and the source/drain in the active region of the substrate;

forming a silicide layer over a surface of the elevated source/drain region.

11. A process as recited in claim 10, further comprising forming an LDD region in the active region of the substrate using the gate electrodes as a mask prior to forming the oxide layer.

15. A process as recited in claim 10, wherein forming the trench in the oxide layer leaves portions of the oxide layer between edges of the trench and sidewalls of the gate electrodes.

16. A process as recited in claim 10, wherein the oxide layer has a thickness greater than a thickness of the gate electrodes.

17. A process of forming a semiconductor device, comprising:

forming a plurality of gate electrodes on a substrate, an active region of the substrate being defined by adjacent walls of two gate electrodes;

forming an insulating layer having a thickness greater than a thickness of the gate electrodes over the gate electrodes and the active region;

removing portions of the insulating layer to form a trench over a portion of the active region of the substrate and leaving portions of the insulating layer between edges of the trench and sidewalls of the gate electrodes;

filling the trench with a polysilicon material; and

doping the polysilicon material to form an elevated active region above the active region of the substrate.

18. A process as recited in claim 17, further comprising implanting a dopant into the active region of the substrate through the trench prior to filling the trench with the polysilicon material.

19. A process as recited in claim 17, wherein doping of the polysilicon material includes diffusing the dopant through the polysilicon material to dope a region in the active region of the substrate.

20. A process as recited in claim 17, wherein the thickness of the insulating layer is about twice the thickness of the gate electrodes.