Dynamic memory device with refresh circuit and refresh method

DC
  • US 5,875,143 A
  • Filed: 11/24/1997
  • Issued: 02/23/1999
  • Est. Priority Date: 07/15/1996
  • Status: Expired due to Term
First Claim
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1. A dynamic memory device comprising:

  • (a) a plurality of storage elements;

    (b) a signal provider for sending refresh signals to said storage elements and for providing addresses of substantially all storage elements; and

    (c) a programmable signal controller coupled to said signal provider for receiving said addresses and for comparing magnitudes of said addresses to a magnitude of a reference address, said programmable signal controller for controlling said signal provider so that, during a particular refresh cycle in which addresses for substantially all storage elements are generated, only a first sub-set of storage elements with addresses in a first magnitude relation to said reference address are refreshed and a second sub-set of storage elements with addresses in a second magnitude relation to said reference address are not refreshed.

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