Semiconductor memory device
First Claim
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1. A semiconductor memory device comprising:
- a memory cell including a capacitor with first and second electrodes and a MOS transistor having a first source/drain, a second source/drain, a floating body sandwiched by said first source/drain and said second source/drain, and a gate formed above said floating body, wherein said first source/drain is connected to said second electrode of said capacitor; and
charge draining means for draining out charge accumulated in the body of said MOS transistor via said second source/drain while the MOS transistor is rendered at an off state.
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Abstract
In a dynamic random access memory, at a time of body-refresh operation, a bit-line potential VBL is set to a body-refresh-potential VBR, and the body-refresh-potential VBR is supplied to bit-line pairs via a bit-line precharging/equalizing circuit 111c, thereby the charge accumulated in the body of the n channel MOS transistor 72cb in a memory cell is drained to the bit-line pairs.
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16 Claims
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1. A semiconductor memory device comprising:
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a memory cell including a capacitor with first and second electrodes and a MOS transistor having a first source/drain, a second source/drain, a floating body sandwiched by said first source/drain and said second source/drain, and a gate formed above said floating body, wherein said first source/drain is connected to said second electrode of said capacitor; and charge draining means for draining out charge accumulated in the body of said MOS transistor via said second source/drain while the MOS transistor is rendered at an off state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor memory device comprising:
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a plurality of memory cells each including a capacitor with first and second electrodes, a MOS transistor having a first source/drain, and a second source/drain, a floating body sandwiched by said first source/drain and said second source/drain, and a gate, wherein said first source/drain is connected to said second electrode of said capacitor; a plurality of bit-line pairs arranged to form a plurality of columns, wherein each of said bit-line pairs is connected to said second source/drains of said memory cells on one of said columns; a plurality of sense-amplifiers each connected to one of said bit-line pairs for amplifying a difference in potential developed in said bit-line pair, and in a body-refresh operation, for setting one of the bit-lines in said bit-line pair at a body-refresh potential while the MOS transistors connected to said one of bit lines are rendered at an off state to drain out charge accumulated in the floating bodies of said MOS transistors to said one of the bit-lines in said bit-line pair; an I/O-line pair; and a plurality of gate circuits each provided between one of said bit-line pairs and said I/Q-line pair, said plurality of gate circuits selectively connecting one of said bit line pairs and said I/O-line pair electrically, and in the body-refresh operation, said plurality of gate circuits electrically connecting a plural number of said bit-line pairs and said I/O-line pair. - View Dependent Claims (12, 13, 14, 15, 16)
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Specification