Method and circuit for self-latching data read lines in the data output path of a semiconductor memory device

• US 5,877,987 A
• Filed: 02/14/1997
• Issued: 03/02/1999
• Est. Priority Date: 02/14/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Merritt, Todd A.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US08/799,357
• Time in Patent Office: 746 Days
• Field of Search: 365/189.05, 365/205, 365/207, 365/208
• US Class Current: 365/189.05
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

A method and circuit for self-latching data read lines that are used to transfer data that is read from a memory array of a memory device to a data output register of the memory device, wherein a self-latching latch circuit is connected to each data read line. The latch circuits are located physically near the output of the memory array, for latching data that is read from the memory array as soon as the data is applied to the data read lines, and prior to the data being latched in the data output register, thereby minimizing the effects of propagation delay so that the memory cycle time can be decreased. In one embodiment wherein the memory is organized in a "x4" configuration, different groups of the data read lines are selected in alternate read cycles, and the data read lines of the non-selected data read group are equilibrated automatically during the read cycle using the conventional test circuits of the memory device.

Claims

1. A data read line latch circuit connected to a data read line of a semiconductor memory device for latching data that is read out of a memory array of the memory device prior to the data being latched in a data output register of the memory device, the data read line latch circuit being located physically in the proximity of the memory array.

2. The data read line latch circuit according to claim 1, which includes a self-latching circuit.

3. The data read line latch circuit according to claim 2, wherein the self-latching circuit comprises a first inverter circuit having an input and an output, and a second inverter circuit having an input and an output, the input of the first inverter circuit being connected to the data read line, the output of the first inverter circuit being connected to the input of the second inverter circuit, and the output of the second inverter circuit being connected to the data read line.

4. A data output path for a semiconductor memory device that includes a memory array for storing data, said data output path comprising:

a plurality of data amplifier circuits located at the output of the memory array for amplifying data read from the memory array;

a data output register for latching data read from the memory array;

a plurality of data read lines coupled between the data amplifier circuits and the data output register for transferring data amplified by the data amplifier circuits to the data output register; and

a plurality of data read line latch circuits, each of the data read line latch circuits being connected to a different one of the data read lines, the data read line latch circuits being located physically adjacent to the data amplifier circuits and being interposed between the data amplifier circuits and the data output register for latching data prior to the data being latched by the data output register.

5. The data output path according to claim 4, wherein each of the data read lines comprises first and second data lines which form a paired data read line, and wherein each data read line latch circuit comprises a first latch circuit connected to the first data line of a paired data read line and a second latch circuit connected to the second data line of the paired data read line.

6. The data output path according to claim 5, wherein a first group of the paired data read lines are selected for use in transferring data from the data amplifier circuits to the data output register during a first read cycle, and a second group of the paired data read lines are selected for use in transferring data from the data amplifier circuits to the data output register during a second read cycle, and including equilibration circuits for equilibrating non-selected data read line pairs during read cycles.

7. The data output path according to claim 6, including a first control circuit for enabling a first plurality of the equilibration circuits to equilibrate the second group of the paired data read lines during the first read cycle, and a second control circuit for enabling a second plurality of the equilibration circuits to equilibrate the first group of the paired data read lines during the second read cycle.

8. The data output path according to claim 7, wherein the first control circuit enables the first plurality of equilibration circuits in response to a first signal that selects the first group of the paired data read lines, and the second control circuit enables the second plurality of equilibration circuits in response to a second signal that selects the first second group of the paired data read lines.

9. A semiconductor memory device comprising:

a memory array for storing data;

a data output register for latching data read from the memory array; and

a data output path for transferring data read from the memory array to the data output register;

the data output path including

a plurality of data amplifier circuits located at the output of the memory array for amplifying data read from the memory array;

a plurality of data read lines coupled between the data amplifier circuits and the data output register for transferring data amplified by the data amplifier circuits to the data output register; and

a plurality of data read line latch circuits, each of the data read line latch circuits being connected to a different one of the data read lines, the data read line latch circuits being located adjacent to the data amplifier circuits for latching data prior to the data being latched by the data output register.

10. The memory device according to claim 9, wherein each of the data read lines comprises first and second data lines which form a paired data read line, and wherein each data read line latch circuit comprises a first latch circuit connected to a first data line of a paired data read line and a second latch circuit connected to a second data line of the paired data read line.

11. The memory device according to claim 10, wherein a first group of the paired data read lines are selected for use in transferring data from the data amplifier circuits to the data output register during a first read cycle, and a second group of the paired data read lines are selected for use in transferring data from the data amplifier circuits to the data output register during a second read cycle, and including a plurality of equilibration circuits for equilibrating non-selected data read line pairs during read cycles.

12. The memory device according to claim 11, including a first control circuit for enabling a first plurality of the equilibration circuits to equilibrate the second group of the paired data read lines during the first read cycle, and a second control circuit for enabling a second plurality of equilibration circuits to equilibrate the first group of the paired data read lines during the second read cycle.

13. The memory device according to claim 12, wherein the first control circuit is enabled automatically in response to selection of the first group of the selected paired data read lines and the second control circuit is enabled automatically in response to selection of the second group of the selected paired data read lines.

14. The memory device according to claim 13, wherein the first and second control circuits are responsive to address signals for enabling the first and second pluralities of equilibration circuits.

15. A semiconductor memory device comprising:

a memory array for storing data;

a data output register for latching data read from the memory array;

a plurality of data read lines for transferring data read from the memory array to the data output register;

a plurality of data read line latch circuits, including a data read line latch circuit individually connected to each data read line for latching data applied to the data read lines prior to the data being latched by the data output register;

memory access circuitry for selecting a first group of the data read lines for transferring data read from the memory array to the data output register during a first read cycle, and for selecting a second group of the data read lines for transferring data read from the memory array to the data output register during a second read cycle; and

a plurality of equilibration circuits for equilibrating non-selected data read line pairs during read cycles.

16. The memory device according to claim 15, wherein a first group of the equilibration circuits are enabled automatically in response to selection of the first group of the selected data read lines, the first group of the equilibration circuits equilibrating the second group of the paired data read lines during the first read cycle, and wherein a second group of the equilibration circuits are enabled automatically in response to selection of the second group of the selected data read lines, the second group of the equilibration circuits equilibrating the first group of the paired data read lines during the second read cycle.

17. A method for self-latching data read lines that transfer data read from a memory array of a semiconductor memory device to a data output register of the memory device, said method comprising:

connecting a latch circuit to each of the data read lines in the proximity of the memory array; and

causing the latch circuit to respond to data read from the memory array and latch the data into the latch circuit so that the data is latched into the latch circuit prior to being latched into the data output register.

18. A method for transmitting data read from a memory array of a semiconductor memory device to a data output register of the memory device, wherein data read from the memory array is amplified by a data amplifier that is coupled to the data output register through a data read line, said method comprising:

connecting a data read line latch circuit to the data read line at the output of the data amplifier circuit;

latching the data amplified by the data amplifier circuit into the data read line latch circuit; and

subsequently latching the data latched in the data read line latch circuit into the data output register.

19. The method according to claim 18, including selecting certain data read lines for use in transferring data from the memory array to the data output register during a given read cycle and equilibrating the non-selected data read lines during the given read cycle.