Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs
DCFirst Claim
1. A method for analyzing a semiconductor chip design, comprising the steps of:
- dividing the semiconductor chip design into a plurality of blocks;
performing a block level verification based on an assumption that full voltage is being supplied to the blocks;
modeling the blocks according to a resistor and capacitor network;
simplifying the resistor and capacitor network into an equivalent circuit;
determining voltage drops corresponding to the equivalent circuit;
analyzing the blocks with the voltage being supplied to the blocks reduced according to the determined voltage drops.
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Abstract
The present invention pertains to a method for analyzing a semiconductor chip design for determining potential voltage drop and electromigration problems. Initially, the semiconductor chip design is divided into a plurality of blocks. A block level verification is then performed based on the assumption that full voltage is being supplied to each of the blocks. Next, the blocks are modeled by an equivalent RC network. This RC network is then reduced into a simpler representation. The voltage drops are determined based on the reduced, equivalent model. The blocks are then reanalyzed with the supply voltage input to the blocks reduced according to the calculated voltage drops. Thereby, a more realistic simulation can be achieved.
33 Citations
22 Claims
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1. A method for analyzing a semiconductor chip design, comprising the steps of:
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dividing the semiconductor chip design into a plurality of blocks; performing a block level verification based on an assumption that full voltage is being supplied to the blocks; modeling the blocks according to a resistor and capacitor network; simplifying the resistor and capacitor network into an equivalent circuit; determining voltage drops corresponding to the equivalent circuit; analyzing the blocks with the voltage being supplied to the blocks reduced according to the determined voltage drops. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A computer-readable medium having stored thereon instructions for causing a computer to implement computer-controlled reliability analysis of a semiconductor chip design, comprising the steps of:
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performing a block level verification, wherein the semiconductor chip design is divided into a plurality of blocks and a full voltage supply is assumed to be input to each power connection point corresponding to the blocks; modeling the blocks by equivalent RC networks; performing a simulation on the modeled blocks to determine voltage drops and current values; analyzing the blocks according to the voltage drops and current values to determine whether there are any performance problems with the chip design. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A computer system for implementing computer-controlled reliability analysis of a semiconductor chip design, comprising:
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a memory for storing a netlist and a layout corresponding to a schematic of the semiconductor chip; a processor coupled to the memory for performing a block level verification, wherein the layout is divided into a plurality of blocks and a full voltage supply is assumed to be input to each power connection point corresponding to the blocks, the processor models the blocks by equivalent RC networks and performs a simulation on the modeled blocks to determine voltage drops and current values, wherein the blocks are analyzed according to the voltage drops and current values to determine whether there are any violations with the chip design; a display coupled to the processor for displaying the violations. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification