Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs

  • US 5,878,053 A
  • Filed: 06/09/1997
  • Issued: 03/02/1999
  • Est. Priority Date: 06/09/1997
  • Status: Expired due to Term
First Claim
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1. A method for analyzing a semiconductor chip design, comprising the steps of:

  • dividing the semiconductor chip design into a plurality of blocks;

    performing a block level verification based on an assumption that full voltage is being supplied to the blocks;

    modeling the blocks according to a resistor and capacitor network;

    simplifying the resistor and capacitor network into an equivalent circuit;

    determining voltage drops corresponding to the equivalent circuit;

    analyzing the blocks with the voltage being supplied to the blocks reduced according to the determined voltage drops.

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