Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors on write to program counter of one processor

• US 5,881,272 A
• Filed: 09/02/1997
• Issued: 03/09/1999
• Est. Priority Date: 11/17/1989
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Balmer, Keith
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/922,152
• Time in Patent Office: 553 Days
• Field of Search: 395/553, 395/200.78, 395/381, 395/800.21
• US Class Current: 713/375
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/355 Indexed addressing
• CPC Class Codes: G06F 9/3832 Value prediction for operands; operand history buffers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.

Claims

1. A synchronization system comprising:

a synchronization bus having a plurality of bus lines;

a plurality of processors, equal in number to the number of bus lines in said synchronization bus, each processor fetching and executing instructions independently of other processors, each processor including

a program counter register storing an address of a next instruction for fetching said next instruction,

a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor,

an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating an okay to synchronize signal on said corresponding line of said synchronization bus when said processor is ready to fetch a next instruction, said okay to synchronize circuit inhibiting generation of said okay to synchronize signal during an interval from the storing of a changed address in said program counter other than a next sequential address until execution of an instruction at said changed address,

a synchronization logic unit connected to said synchronization bus, said program counter register and said synchronization register for inhibiting the fetching of said next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus, thereafter permitting the fetching of said next instruction by said program counter register, and

an execution unit for executing fetched instructions, whereby each processor is synchronized to said other of said processors indicated in said synchronization register on an instruction by instruction basis.

2. The synchronizing system of claim 1, wherein:

each processor further includes

a data register file including a plurality of data registers for storing data,

a bus connected to said synchronization register and said data register file for moving data from an instruction specified one of said plurality of data registers to said synchronization register in response to a register move instruction specifying one of said plurality of data registers as a source and said synchronization register as a destination.

3. The synchronizing system of claim 1, wherein:

each processor further includes

a data register file including a plurality of data registers for storing data,

a bus connected to said synchronization register and said data register file for moving data from said synchronization register to an instruction specified one of said plurality of data registers in response to a register move instruction specifying said synchronization register as a source and one of said plurality of data registers as a destination.

4. The synchronizing system of claim 1, wherein:

each processor further includes

a memory including an address input and a data port for storing data at a plurality of addressable memory storage locations;

an address generator connected to said address input of said memory, said address generator generating an address corresponding to one of said plurality of addressable memory storage locations of said memory, and

a data bus connected to said synchronization register and said data port of said memory for moving data from said synchronization register to one of said plurality of addressable memory storage locations of said memory corresponding to said address generated by said address generator in response to a register store instruction specifying said synchronization register as a destination.

5. The synchronizing system of claim 1, wherein:

each processor further includes

a memory including an address input and a data port for storing data at a plurality of addressable memory storage locations,

an address generator connected to said address input of said memory, said address generator generating an address corresponding to one of said plurality of addressable memory storage locations of said memory, and

a data bus connected to said synchronization register and said data port of said memory for moving data from one of said plurality of addressable memory storage locations of said memory corresponding to said address generated by said address generator to said synchronization register in response to a register load instruction specifying said synchronization register as a destination.

6. The synchronization system as claimed in claim 1, wherein:

each processor further includes

a synchronization flag memory connected to said synchronization control logic having stored therein an indication of whether said processor is in a synchronized mode or in an unsynchronized mode, and

wherein said synchronization logic unit

inhibits the fetching the next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus when said synchronization flag memory indicates said synchronized mode, and

permits the fetching of the next instruction by said program counter register regardless of the status of said synchronization bus and said synchronization register when said synchronization flag memory indicates said unsynchronized mode.

7. The synchronization system as claimed in claim 6, wherein:

said execution unit of each processor includes a first instruction responsive circuit for loading an indication of the synchronized mode into said synchronization flag memory in response to execution of a lock instruction, whereby said lock instruction begins said synchronized mode.

8. The synchronization system as claimed in claim 6, wherein:

said execution unit of each processor includes a second instruction responsive circuit for loading an indication of the unsynchronized mode into said synchronization flag memory in response to execution of a unlock instruction, whereby said unlock instruction ends said synchronized mode.

9. The synchronization system of claim 6, wherein:

said execution unit of each processor causes said synchronization flag memory to enter said unsynchronized mode for an interval from the storing of said changed address in said program counter until execution of an instruction at said changed address.

10. The synchronization system of claim 1, wherein:

each processor further includes

a data register file including a plurality of data registers for storing data,

a bus connected to said program counter and said data register file,

said execution unit moving a branch address from an instruction specified one of said plurality of data registers to said program counter in response to a branch instruction specifying one of said plurality of data registers as a source,

said okay to synchronize circuit inhibiting generation of said okay to synchronize signal during an interval from the execution of a branch instruction until execution of an instruction at said branch address.

11. The synchronizing system of claim 10, wherein:

each processor further includes

a return address register connected to said program counter,

said execution unit connected to said return address register for storing a return address corresponding to a next sequential instruction to that stored in said program counter in response to a subroutine call instruction.

12. The synchronizing system of claim 11, wherein:

each processor wherein

said execution unit storing said return address from said return address register in said program counter in response to a subroutine return instruction, and

said okay to synchronize circuit inhibiting generation of said okay to synchronize signal during an interval from the execution of a subroutine return instruction until execution of an instruction at said return address.

13. The method of operating a computer system having a plurality of processors in synchronism, each of the processors independently fetching and executing instructions, said method comprising the steps of:

storing in a program counter an address of a next sequential instruction to be executed by said processor;

generating at each processor a ready signal when said processor is ready to fetch an instruction;

storing at each processor an indication of other processor or processors to which said processor is to be synchronized;

inhibiting fetching a next instruction at each processor until said processor receives said ready signal from all other processor or processors to which said processor is to be synchronized according to said stored indication and thereafter fetching said instruction at each processor;

inhibiting fetching an instruction at each processor during an interval from the storing of a changed address in a program counter other than a next sequential address until execution of an instruction at said changed address at any one processor from all other processor or processors to which said processor is to be synchronized according to said stored indication; and

executing fetched instructions at each processor, whereby each processor is synchronized with said other processor or processors according to said stored indication on an instruction by instruction basis.

14. The method of claim 13, wherein:

said step of storing at each processor an indication of other processor or processors to which said processor is to be synchronized stores said indication in a synchronization register; and

further comprising the step of moving data from an instruction specified one of a plurality of data registers to said synchronization register in response to a register move instruction specifying one of said plurality of data registers as a source and said synchronization register as a destination.

15. The method of claim 13, wherein:

said step of storing at each processor an indication of other processor or processors to which said processor is to be synchronized stores said indication in a synchronization register; and

further comprising the step of moving data from said synchronization register to an instruction specified one of a plurality of data registers in response to a register move instruction specifying said synchronization register as a source and one of said plurality of data registers as a destination.

16. The method of claim 13, wherein:

said step of storing at each processor an indication of other processor or processors to which said processor is to be synchronized stores said indication in a synchronization register; and

further comprising the step of moving data from said synchronization register to one of a plurality of addressable memory storage locations of a memory in response to a register store instruction specifying said synchronization register as a source.

17. The method of claim 13, wherein:

said step of storing at each processor an indication of other processor or processors to which said processor is to be synchronized stores said indication in a synchronization register; and

further comprising the step of moving data from one of a plurality of addressable memory storage locations of a memory to said synchronization register in response to a register load instruction specifying said synchronization register as a destination.

18. The method of claim 13, wherein:

said step of storing at each processor an indication of other processor or processors to which the processor is to be synchronized includes specifying the other processor or processors to which the processor is to be synchronized in response to execution of a first instruction by the processor.

19. The method as claimed in claim 18, wherein:

said step of specifying the other processor or processors to which each processor is to be synchronized includes specifying via a first instruction executed by said processor a subset of the other processors to which said processor is to be synchronized, said processor operating asynchronously with respect to other processors not in said subset.

20. The method as claimed in claim 18, wherein:

said step of specifying the other processor or processors to which said processor is to be synchronized includes specifying via a first instruction executed by said processor a plurality of groups of processors to be synchronized with respect to other processors in the same group and operating each group of processors asynchronously with respect to other groups of processors.

21. The method as claimed in claim 13, further comprising the step of:

storing at each processor an indication of a synchronized mode or an unsynchronized mode; and

said step of inhibiting fetching an instruction at each processor until said processor receives said ready signal from all other processor or processors to which that processor is to be synchronized according to said stored indication includes

inhibiting fetching an instruction at each processor until said processor receives said ready signal from all other processor or processors to which that processor is to be synchronized according to said stored indication when said processor stores an indication of the synchronized mode, and

permitting fetching an instruction at each processor regardless of the status of the ready signal of other processors when said processor stores an indication of the unsynchronized mode.

22. The method as claimed in claim 21, wherein:

said step of storing at each processor an indication of a synchronized mode or an unsynchronized mode includes storing an indication of the synchronized mode in response to execution of a lock instruction by said processor.

23. The method as claimed in claim 21, wherein:

said step of storing at each processor an indication of a synchronized mode or an unsynchronized mode includes storing an indication of the unsynchronized mode in response to execution of an unlock instruction by said processor.

24. The method of claim 21, wherein:

said step of storing at each processor an indication of a synchronized mode or an unsynchronized mode includes storing an indication of the unsynchronized mode for an interval from the storing of said changed address in said program counter until execution of an instruction at said changed address.

25. The method of claim 13, further comprising the step of:

moving a branch address from an instruction specified one of a plurality of data registers to said program counter in response to a branch instruction specifying one of said plurality of data registers as a source; and

inhibiting fetching an instruction at each processor during an interval from the execution of a branch instruction until execution of an instruction at said branch address at any one processor from all other processor or processors to which that processor is to be synchronized according to said stored indication.

26. The method of claim 25, further comprising the step of:

storing a return address corresponding to a next sequential instruction to that stored in said program counter in response to a subroutine call instruction.

27. The method of claim 26, wherein:

inhibiting fetching a next instruction at each processors during an interval from the execution of a subroutine return instruction until execution of an instruction at said return address at any one processor from all other processor or processors to which that processor is to be synchronized according to said stored indication.