High frequency switching circuit

• US 5,883,541 A
• Filed: 03/05/1997
• Issued: 03/16/1999
• Est. Priority Date: 03/05/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Miya, Tatsuya, Tahara, Kazuhiro
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US08/811,931
• Time in Patent Office: 741 Days
• Field of Search: 327/365, 327/374-377, 327/379, 327/389, 327/391, 327/404, 327/427, 327/434, 327/437, 327/308, 333/81 R, 333/103, 333/104, 333/262, 333/81 A, 333/32
• US Class Current: 327/434
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A high frequency switching circuitry comprising the following elements. At least one input signal terminal is provided into which an input signal is inputted. An output signal terminal is also provided, from which an output signal is outputted. A first resistive switching circuit is connected between the input signal terminal and a first node. The first resistive switching circuit has first and second signal transmission channels having first and second resistances. The second resistance of the second channel is much higher than the first resistance of the first channel. The first resistive switching circuit switches the first and second signal transmission channels. A first switching element is connected between the first node and the output terminal. A second switching element is connected in series between the first node and a ground line. It is important that the second resistance of the second signal transmission channel of the first resistive switching circuit is almost equal to a difference of an ON-resistance of the second switching element from an impedance of a signal source of the high frequency switching circuitry.

Claims

1. A high frequency switching circuitry comprising:

at least one input signal terminal into which an input signal is inputted;

an output signal terminal from which an output signal is outputted;

first and second field effect transistors connected in series between said input signal terminal and said output signal terminal, said first field effect transistor being coupled to said input signal terminal, said second field effect transistor being coupled to said output signal terminal, said first and second field effect transistors being directly connected to each other via a first node;

a third field effect transistor directly connected at said first node so that said third field effect transistor is connected in series between said first node and a ground line;

a first gate control signal line on which a first gate control signal is applied, said first gate control signal line being connected to both gates of said first and second field effect transistors for transmitting said first gate control signal to said gates of said first and second field effect transistors;

a second gate control signal line on which a second gate control signal is applied, said second gate control signal line being connected to a gate of said third field effect transistor; and

a first resistor connected in parallel to said first field effect transistor between said input signal terminal and said first node, wherein said first resistor has a first resistance which is approximately equal to a difference of an ON-resistance of said third field effect transistor from an output impedance of a first signal source of said high frequency switching circuitry.

2. The high frequency switching circuitry of claim 1, further comprising:

a secondary input signal terminal into which a second input signal is inputted;

fourth and fifth field effect transistors connected in series between said secondary input signal terminal and said output signal terminal, said fourth field effect transistor being coupled to said secondary input signal terminal, said fifth field effect transistor being coupled to said output signal terminal, said fourth and fifth field effect transistors being directly connected to each other via a second node;

a sixth field effect transistor connected in series between said second node and a ground line; and

a second resistor connected in parallel to said fourth field effect transistor between said secondary input signal terminal and said second node,

wherein said second resistor has a second resistance which is approximately equal to a difference of an ON-resistance of said sixth field effect transistor from an output impedance of a second signal source of said high frequency switching circuitry.

3. The high frequency switching circuitry of claim 2, wherein said first gate control signal is connected to a gate of said sixth field effect transistor, said second gate control signal being connected to gates of said fourth and fifth field effect transistors,

wherein said first gate control signal and second gate control signal are designed and adapted:

1) to turn ON said first, second and sixth field effect transistors while concurrently keeping said third, fourth and fifth field effect transistors biased OFF, and

     2) to turn ON said third, fourth and fifth field effect transistors while concurrently keeping said first, second and sixth field effect transistors biased OFF.

4. The high frequency switching circuitry of claim 1, further comprising a third resistor connected in parallel to said second field effect transistor between said output signal terminal and said first node, wherein said third resistor has been sized to have a third resistance which is approximately equal to said first resistance of said first resistor.

5. A high frequency switching circuitry comprising:

at least one input signal terminal into which an input signal is inputted;

an output signal terminal from which an output signal is outputted;

a first resistive switching circuit connected between said input signal terminal and a first node, said first resistive switching circuit having first and second signal transmission channels having first and second resistances, said second resistance of said second channel being much higher than said first resistance of said first channel, said first resistive switching circuit switching said first and second signal transmission channels;

a first switching element, connected between said first node and said output terminal, said first resistive switching circuit and said first switching element being directly connected to each other via said first node,

a second switching element directly connected at said first node so that said second switching element is connected in series between said first node and a ground line,

wherein said second resistance of said second signal transmission channel of said first resistive switching circuit is approximately equal to a difference of an ON-resistance of said second switching element from an output impedance of a first signal source of said high frequency switching circuitry.

6. The high frequency switching circuitry as claimed in claim 5, wherein said first resistive switching circuit comprises:

a third switching element connected between said input signal terminal and said first node; and

a first resistor connected in parallel to said third switching element between said input signal terminal and said first node.

7. The high frequency switching circuitry as claimed in claim 6, wherein said first, second and third switching elements comprise first, second and third field effect transistors;

and

further comprising first and second gate control signal lines on which first and second gate control signals are transmitted, said first gate control signal line being connected to gates of said first and third field effect transistors, said second gate control signal line being connected to a gate of said second field effect transistor.

8. The high frequency switching circuitry of claim 5, further comprising:

a secondary input signal terminal into which a second input signal is inputted;

a second resistive switching circuit connected between said secondary input signal terminal and a second node, said second resistive switching circuit having third and fourth signal transmission channels having third and fourth resistances, said fourth resistance of said fourth channel being much higher than said third resistance of said third channel, said second resistive switching circuit switching said third and fourth signal transmission channels;

a fourth switching element connected between said second node and said output terminal;

a fifth switching element connected in series between said second node and a ground line,

wherein said fourth resistance of said fourth signal transmission channel of said second resistive switching circuit is approximately equal to a difference of an ON-resistance of said fourth switching element from an output impedance of a second signal source of said high frequency switching circuitry.

9. The high frequency switching circuitry as claimed in claim 8, wherein said second resistive switching circuit comprises:

a sixth switching element connected between said second input signal terminal and said second node; and

a second resistor connected in parallel to said sixth switching element between said input signal terminal and said second node.

10. The high frequency switching circuitry as claimed in claim 9, wherein said fourth, fifth and sixth switching elements comprise fourth, fifth and sixth field effect transistors;

and

further comprising first and second gate control signal lines on which first and second gate control signals are transmitted, said second gate control signal line being connected to gates of said fourth and sixth field effect transistors, said first gate control signal line being connected to a gate of said fifth field effect transistor.

11. A high-frequency switching circuit comprising:

a first input signal terminal for receiving an input signal;

an output signal terminal for providing an output signal;

first and second field effect transistors connected in series between said first input signal terminal and said output signal terminal, said first field effect transistor being coupled to said first input signal terminal, said second field effect transistor being coupled to said output signal terminal, said first and second field effect transistors being directly connected at a first node;

a third field effect transistor directly connected at said first node so that said third field effect transistor is connected in series between said first node and a ground line to provide a to-ground current path from said first node having a resistance equal to an ON-resistance of said third field effect transistor;

a first gate control signal line for applying a first gate control signal, said first gate control signal line being connected to both gates of said first and second field effect transistors for transmitting the first gate control signal to said gates of said first and second field effect transistors so that the first gate control signal turning said first and second field effect transistors ON forms a first input-to-output current path from said first input terminal to said output terminal having a resistance equal to an ON-resistance of said first and second field effect transistors;

a second gate control signal line for applying a second gate control signal, said second gate control signal line being connected to a gate of said third field effect transistor;

a first resistor connected in a branch, said branch parallel to said first field effect transistor between said first input signal terminal and said first node, wherein said branch has a first branch resistance determined by said first resistor, and said first resistor has a first resistance which is approximately equal to a difference of said ON-resistance of said third field effect transistor from an output impedance of a first signal source applied at said first input signal terminal;

a second input signal terminal for receiving a second input signal;

fourth and fifth field effect transistors connected in series between said second input signal terminal and said output signal terminal, said fourth field effect transistor being coupled to said second input signal terminal, said fifth field effect transistor being coupled to said output signal terminal, said fourth and fifth field effect transistors being directly connected to each other via a second node;

a sixth field effect transistor connected at said second node so that said sixth field effect transistor is connected in series between said second node and a ground line to provide a to-ground current path from said second node having a resistance equal to an ON-resistance of said sixth field effect transistor;

said first gate control signal being connected to a gate of said sixth field effect transistor, said second gate control signal being connected to gates of said fourth and fifth field effect transistors; and

a second resistor connected in a second branch, said second branch parallel to said fourth field effect transistor between said second input signal terminal and said second node, wherein said second branch has a second branch resistance determined by said second resistor, and said second resistor has a second resistance which is approximately equal to a difference of said ON-resistance of said sixth field effect transistor from an output impedance of a second signal source applied at said second input signal terminal;

wherein said first gate control signal and second gate control signal are designed and adapted;

     1) to turn ON said first, second and sixth field effect transistors while concurrently keeping said third, fourth and fifth field effect transistors biased OFF, and

     2) to turn ON said third, fourth and fifth field effect transistors while concurrently keeping said first, second and sixth field effect transistors biased OFF.