Amplifier using a single polarity power supply and including depletion mode FET and negative voltage generator

• US 5,892,400 A
• Filed: 12/12/1996
• Issued: 04/06/1999
• Est. Priority Date: 12/15/1995
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Anadigics Incorporated (Coherent Corp.)
• Inventors: Bayruns, Robert J., van Saders, John
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/764,350
• Time in Patent Office: 845 Days
• Field of Search: 330/277, 330/296, 327/535, 327/536, 327/537, 327/538, 327/539, 323/313, 323/314
• US Class Current: 330/277
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 1/305 in case of switching on or off of a power supply
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.

Claims

1. An amplifier operating with a single polarity power supply, comprising:

an amplifying stage including at least one depletion-mode FET for amplifying an input ac signal, said FET having a gate coupled to receive said input ac signal, a source connected to ground and a drain coupled to receive a positive voltage; and

a negative voltage generator for providing a negative voltage to bias the gate of said FET,

said negative voltage generator comprising a multivibrator generating first and second clock signals, a charge pump receiving said clock signals and operating to produce said negative voltage, and means for providing said negative voltage as a low potential reference to said multivibrator such that said clock signals include a negative potential period and as a result, said charge pump operating in a power efficient manner.

2. The amplifier of claim 1 further comprising means for providing said clock signals from said multivibrator to said charge pump, and said means including an RC network.

3. The amplifier of claim 1 further comprising a negative voltage regulator for regulating said negative voltage to a desired value and for providing a regulated negative voltage to the gate of said depletion-mode FET.

4. The amplifier of claim 3 wherein said negative voltage generator is a monolithic integrated circuit, and said regulator and said amplifying stage form another monolithic integrated circuit, and said amplifier is a hybrid device including said two monolithic integrated circuits.

5. The amplifier of claim 3 wherein said negative voltage generator, said negative voltage regulator and said amplifying stage form a monolithic GaAs integrated circuit.

6. The amplifier of claim 1 wherein said multivibrator comprises first and second inverters having input and output terminals,

a first capacitive means coupling between the input terminal of said first inverter to the output terminal of said second inverter,

a second capacitive means coupling between the input terminal of said second inverter and the output terminal of said first inverter,

a first resistive means coupled between the input terminal of said first inverter and ground, and

a second resistive means coupled between the input terminal of said second inverter and the negative voltage.

7. The amplifier of claim 6 wherein said first inverter comprises a first FET having a source connected to ground, a drain connected to a first load means and to the output terminal of said first inverter, and gate connected to the input terminal of said first inverter, and

wherein said second inverter comprises a second FET having a source connected to the negative potential, a drain connected to a second load means and to the output terminal of said second inverter, and a gate connected to the input terminal of said second inverter.

8. The amplifier of claim 7 wherein said first load means includes a third FET having gate and source connected together and to the drain of said first FET, and a drain coupled to a positive terminal of said power supply, and wherein said second load means includes a fourth FET having gate and source connected together and to the drain of said second FET, and a drain coupled to the positive terminal of said power supply.

9. The amplifier of claim 1 wherein said charge pump comprises a first electronic switch having a first terminal for connection to a positive terminal of said power supply and a second terminal,

a second electronic switch having a first terminal connected to the second terminal of said first electronic switch and a second terminal for connection to ground,

a third electronic switch having a first terminal for connection to ground and a second terminal,

a fourth electronic switch having a first terminal connected to the second terminal of said third electronic switch and a second terminal,

a pump capacitor coupled between the second terminal of said first electronic switch and the second terminal of said third electronic switch,

a hold capacitor coupled between the second terminal of the fourth electronic switch and ground,

said clock signals having a pump period and a hold period,

said first and third electronic switches being responsive to said second clock signal, and whereas said second and fourth electronic switches being responsive to said first clock signal, such that said first and third electronic switches being closed and said second and fourth electronic switches being open thereby charging said pump capacitor during said pump period, and

said first and third electronic switches being open and said second and fourth electronic switches being closed thereby transferring charge from said pump capacitor to said hold capacitor during said transfer period.

10. The amplifier of claim 9 wherein said charge pump comprises a first FET having a drain coupled to the positive terminal of said power supply, a gate connected to receive said second clock signal, and a source,

a second FET having a drain coupled to the source of said first FET, a gate connected to receive said first clock signal, and a source coupled to ground,

a third FET having a drain coupled to ground, a gate coupled to receive said second clock signal through a first capacitive means, and a source,

a fourth FET having a drain connected to the source of said third FET, a gate coupled to receive said first clock signal through a second capacitive means and a source,

said pump capacitor being coupled between the sources of said first and third FETs, said hold capacitor being coupled between the source of said fourth FET and ground, and

a first resistive means coupled between the gate and the source of said fourth FET, whereby said negative voltage is provided at the source of said fourth FET.

11. The amplifier of claim 9 wherein said charge pump comprises a first FET having a drain for connection to the positive terminal of said power supply, a gate connected to receive said second clock signal, and a source,

a second FET having a drain connected to the source of said first FET, a gate connected to receive said first clock signal, and a source for connection to ground,

a first diode means having a cathode coupled to ground, and an anode,

a second diode means having an anode coupled to the cathode of said first diode means, and an anode,

said pump capacitor being coupled between the source of said first FET and the anode of said first diode means, and

said hold capacitor being coupled between the anode of said second diode means and ground, whereby said negative voltage is provided at the anode of said second diode means.

12. The amplifier of claim 2 wherein said negative voltage regulator comprises a current source,

a first FET having a drain coupled to said current source, a source for connection to ground, and a gate;

a second FET having a drain coupled to said power supply, a gate coupled to the drain of said first FET, and a source;

a third FET having a drain coupled to the source of said second FET and to the gate of said first FET, a gate and a source connected together and to said negative voltage, whereby the regulated negative voltage is provided at the drain of said third FET.

13. The amplifier of claim 12 further comprising diode means connected between the source of said second FET and the drain of said third FET.

14. The amplifier of claim 2 wherein said negative voltage generator comprises a current source,

a first FET having a drain coupled to said current source, a source coupled to ground, and a gate,

a second FET having a drain coupled to said power supply, a gate coupled to the drain of said first FET, and a source,

a third FET having a drain coupled to the source of said second FET, a gate and a source connected together and to said negative voltage, the drain of said third FET being resistively coupled to the gate of said depletion-mode FET in said amplifying stage, and the gate of said first FET being resistively coupled to the gate of said depletion-mode FET in said amplifying stage, whereby the effect of increased temperature on the performance of said regulator is reduced.

15. The amplifier of claim 14 wherein said current source comprises a resistor coupled between said power supply and the drain of said first FET.

16. The amplifier of claim 15 wherein said depletion-mode FET in the amplifying stage and said first FET have substantially the same pinch-off characteristics, and the gate-width of said first FET is such that said negative voltage regulator provides a desired regulated negative voltage to bias said depletion-mode FET.

17. The amplifier of claim 14 wherein said current source comprises a fourth FET having a drain coupled to said power supply, a gate and a source connected together and to the drain of said first FET.

18. The amplifier of claim 17 wherein said depletion-mode FET in the amplifying stage and said first and fourth FETs have substantially the same pinch-off characteristics, and the gate-width of said first FET is a predetermined factor times the gate-width of said fourth FET, whereby said depletion mode FET is biased at substantially its characteristic zero-bias saturation current divided by said predetermined factor.

19. The amplifier of claim 18 wherein the predetermined factor is 2, whereby said depletion-mode FET in said amplifying stage is biased at substantially one half of said characteristic zero-bias current for class A operation.

20. The amplifier of claim 18 wherein the predetermined factor is 4, whereby said depletion-mode FET in said amplifying stage is biased at substantially one quarter of said characteristic zero-bias current for class AB operation.

21. The amplifier of claim 18 wherein the predetermined factor is such that said depletion-mode FET in said amplify stage is biased around or below pinch-off for class B operation.

22. The amplifier of claim 21 further comprising diode means connected between the source of said second FET and the drain of said third FET.

23. A negative voltage generator operating with a single power supply comprising:

a multivibrator generating first and second clock signals;

a charge pump receiving said first and second clock signals and operating to generate a negative voltage; and

means for providing said negative voltage as a low reference potential to said multivibrator such that said clock signals generated by said multivibrator includes a negative potential period and as a result, said charge pump operating in a power efficient manner.

24. The negative voltage generator of claim 23 further comprising means for providing said first and second clock signals from said multivibrator to said charge pump, and said means including an RC network.

25. The negative voltage generator of claim 23 wherein said multivibrator comprises first and second inverters having input and output terminals,

a first capacitive means coupling between the input terminal of said first inverter to the output terminal of said second inverter,

a second capacitive means coupling between the input terminal of said second inverter and the output terminal of said first inverter,

a first resistive means coupled between the input terminal of said first inverter and ground, and

a second resistive means coupled between the input terminal of said second inverter and the negative voltage.

26. The negative voltage generator of claim 25 wherein said first inverter comprises a first FET having a source connected to ground, a drain connected to a first load means and to the output terminal of said first inverter, and gate connected to the input terminal of said first inverter, and

wherein said second inverter comprises a second FET having a source connected to the negative potential, a drain connected to a second load means and to the output terminal of said second inverter, and a gate connected to the input terminal of said second inverter.

27. The negative voltage generator of claim 26 wherein said first load means includes a third FET having gate and source connected together and to the drain of said first FET, and a drain coupled to a positive terminal of said power supply, and wherein said second load means includes a fourth FET having gate and source connected together and to the drain of said second FET, and a drain coupled to the positive terminal of said power supply.

28. The negative voltage generator of claim 23 wherein said charge pump comprises a first electronic switch having a first terminal for connection to a positive terminal of said power supply and a second terminal,

a second electronic switch having a first terminal connected to the second terminal of said first electronic switch and a second terminal for connection to ground,

a third electronic switch having a first terminal for connection to ground and a second terminal,

a fourth electronic switch having a first terminal connected to the second terminal of said third electronic switch and a second terminal,

a pump capacitor coupled between the second terminal of said first electronic switch and the second terminal of said third electronic switch,

a hold capacitor coupled between the second terminal of the fourth electronic switch and ground, said clock signals having a pump period and a hold period,

said first and third electronic switches being responsive to said second clock signal, and whereas said second and fourth electronic switches being responsive to said first clock signal, such that said first and third electronic switches being closed and said second and fourth electronic switches being open thereby charging said pump capacitor during said pump period, and

said first and third electronic switches being open and said second and fourth electronic switches being closed thereby transferring charge from said pump capacitor to said hold capacitor during said transfer period.

29. The negative voltage generator of claim 28 wherein said charge pump comprises a first FET having a drain coupled to the positive terminal of said power supply, a gate connected to receive said second clock signal, and a source,

a second FET having a drain coupled to the source of said first FET, a gate connected to receive said first clock signal, and a source coupled to ground,

a third FET having a drain coupled to ground, a gate coupled to receive said second clock signal through a first capacitive means, and a source,

a fourth FET having a drain connected to the source of said third FET, a gate coupled to receive said first clock signal through a second capacitive means and a source,

said pump capacitor being coupled between the sources of said first and third FETs,

said hold capacitor being coupled between the source of said fourth FET and ground, and

a first resistive means coupled between the gate and the source of said fourth FET, whereby said negative voltage is provided at the source of said fourth FET.

30. The negative voltage generator of claim 28 herein said charge pump comprises a first FET having a drain for connection to the positive terminal of said power supply, a gate connected to receive said second clock signal, and a source,

a second FET having a drain connected to the source of said first FET, a gate connected to receive said first clock signal, and a source for connection to ground,

a first diode means having a cathode coupled to ground, and an anode,

a second diode means having an anode coupled to the cathode of said first diode means, and an anode,

said pump capacitor being coupled between the source of said first FET and the anode of said first diode means, and

said hold capacitor being coupled between the anode of said second diode means and ground, whereby said negative voltage is provided at the anode of said second diode means.