Method and apparatus for handling overflow and underflow in processing floatingpoint numbers
First Claim
1. A method for processing floatingpoint numbers, each floatingpoint number having at least a sign portion, an exponent portion and a mantissa portion, comprising the steps of:
 converting a floatingpoint number memory register representation to a floatingpoint register representation;
rounding the converted floatingpoint number;
performing an arithmetic computation upon said rounded number resulting in a new floatingpoint value; and
converting the resulting new floatingpoint register value to a floatingpoint memory register representation.
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Abstract
A method for processing floatingpoint numbers, each floatingpoint number having at least sign portion, an exponent portion and a mantissa portion, comprising the steps of converting a floatingpoint number memory register representation to a floatingpoint register representation; rounding the converted floatingpoint number; performing an arithmetic computation upon said rounded number resulting in a new floatingpoint value; and converting the resulting new floatingpoint register value to a floatingpoint memory register representation. An apparatus for processing floatingpoint numbers comprising means for converting a floatingpoint value from a random access memory register to a floatingpoint unit register; means for selecting the type of accuracy required of the converted value; means for selecting the type of rounding required of the converted floatingpoint value; means for performing an arithmetic operation upon at least one converted floatingpoint value based upon said selected accuracy and rounding; means for chopping the result of the arithmetic operation to fit a mantissa portion of a floatingpoint value; and means for converting the resulting floatingpoint value from the floatingpoint register representation to the random access memory representation.
125 Citations
28 Claims

1. A method for processing floatingpoint numbers, each floatingpoint number having at least a sign portion, an exponent portion and a mantissa portion, comprising the steps of:

converting a floatingpoint number memory register representation to a floatingpoint register representation; rounding the converted floatingpoint number; performing an arithmetic computation upon said rounded number resulting in a new floatingpoint value; and converting the resulting new floatingpoint register value to a floatingpoint memory register representation.  View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)


21. A method for processing floatingpoint numbers from memory register format to arithmetic unit register format and back, each floatingpoint number having at least a sign portion, an exponent portion and a mantissa portion, comprising the steps of:

selecting a primary load control mode for a memory register floatingpoint number to be converted; testing for a memory value state by accessing bit statuses of the sign portion, exponent portion and mantissa portion of the memory register floatingpoint number; converting as required by said primary load control mode the result of said testing of the memory value state into the arithmetic unit register; selecting a primary arithmetic control mode for an arithmetic register floatingpoint number to be computed upon; rounding the arithmetic register floatingpoint number as required by said primary arithmetic control mode; performing an arithmetic operation upon the rounded arithmetic register floatingpoint number; selecting a primary store control mode for said arithmetic register floatingpoint number to be converted; testing the exponent portion of the arithmetic register floatingpoint number; and converting as required by said primary store control mode the result of said testing of the exponent portion into the memory register.


22. An apparatus for processing floatingpoint numbers comprising:

means for converting a floatingpoint value from a random access memory register to a floatingpoint unit register; means for selecting an accuracy required of the converted value; means for selecting a rounding choice required of the converted floatingpoint value; means for performing an arithmetic operation upon at least one converted floatingpoint value based upon said selected accuracy and rounding; means for chopping the result of the arithmetic operation to fit a mantissa portion of a floatingpoint value; and means for converting the resulting floatingpoint value from the floatingpoint register representation to the random access memory representation.  View Dependent Claims (23, 24)


25. An apparatus for processing one or more floatingpoint numbers from memory register format to arithmetic unit register format and back comprising:

one or more priority decoder circuits for converting said floatingpoint number to be loaded from a random access memory register to a floatingpoint unit register; one or more masking circuits for setting the bits of said floatingpoint numbers from the random access memory register to the floatingpoint unit register; one or more priority encoder circuits for rounding said floatingpoint number to be operated upon in said arithmetic logic unit;
an arithmetic logic unit for performing arithmetic operations upon the floatingpoint register numbers;one or more priority encoder circuit for converting and encoding said floatingpoint number to be stored from the floatingpoint unit register to the random access memory register; and one or more masking circuit for setting the bits or said floatingpoint numbers from the floatingpoint unit register to the random access memory register.  View Dependent Claims (26, 27, 28)

1 Specification