Method and apparatus for handling overflow and underflow in processing floating-point numbers

• US 5,892,697 A
• Filed: 12/19/1995
• Issued: 04/06/1999
• Est. Priority Date: 12/19/1995
• Status: Expired due to Term

• Current Assignee: Uniloc Luxembourg S.à r.l. (f/k/a Uniloc Luxembourg S.A.) (Uniloc Corporation Pty. Limited)
• Original Assignee: James Charles Brakefield
• Inventors: Brakefield, James Charles
• Primary Examiner(s): NGO, CHUONG D
• Application Number:
  US08/574,919
• Time in Patent Office: 1,204 Days
• Field of Search: 364/715.03, 364/715.04, 364/736, 364/745, 364/748, 364/749
• US Class Current: 708/496
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/4991 Overflow or underflow
• CPC Class Codes: G06F 7/49947 Rounding
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction

Abstract

A method for processing floating-point numbers, each floating-point number having at least sign portion, an exponent portion and a mantissa portion, comprising the steps of converting a floating-point number memory register representation to a floating-point register representation; rounding the converted floating-point number; performing an arithmetic computation upon said rounded number resulting in a new floating-point value; and converting the resulting new floating-point register value to a floating-point memory register representation. An apparatus for processing floating-point numbers comprising means for converting a floating-point value from a random access memory register to a floating-point unit register; means for selecting the type of accuracy required of the converted value; means for selecting the type of rounding required of the converted floating-point value; means for performing an arithmetic operation upon at least one converted floating-point value based upon said selected accuracy and rounding; means for chopping the result of the arithmetic operation to fit a mantissa portion of a floating-point value; and means for converting the resulting floating-point value from the floating-point register representation to the random access memory representation.

Claims

1. A method for processing floating-point numbers, each floating-point number having at least a sign portion, an exponent portion and a mantissa portion, comprising the steps of:

converting a floating-point number memory register representation to a floating-point register representation;

rounding the converted floating-point number;

performing an arithmetic computation upon said rounded number resulting in a new floating-point value; and

converting the resulting new floating-point register value to a floating-point memory register representation.

2. The method as recited in claim 1 further comprising the step of designating by load primary control logic circuit a mode for said floating-point number representation to be converted, said mode including load an exact number, load with implied maximal accuracy encoding, load with accuracy encoding only for normal numbers and not for underflow or overflow numbers, and load with accuracy for all numbers.

3. The method as recited in claim 2 wherein said mode is convert with accuracy for all numbers, further comprising the step of removing those bits located on the least significant end of the memory mantissa portion and comprised of a variable number of zero bits and a terminating one bit, the least significant bits being a comma code.

4. The method as recited in claim 3 further comprising the step of determining an accuracy value of the memory mantissa portion, said accuracy value being the number of bits between a rightmost one bit and a leading data bit of said mantissa portion.

5. The method as recited in claim 4 further comprising the step of encoding the accuracy of the floating-point register representation, the accuracy value being said memory mantissa accuracy value.

6. The method as recited in claim 1 further comprising the step of utilizing a comma code to represent the degree of underflow and overflow, wherein said comma code is those bits located on the least significant end of the memory mantissa portion and comprised of a variable number of zero bits and a terminating one bit, the least significant bits being said comma code, thereby eliminating denormalization of the mantissa in said step of converting the floating-point number memory register representation to the floating-point register representation and said step of converting the floating-point number register representation to the floating-point memory representation.

7. The method as recited in claim 6 further comprising the step of utilizing said comma code to represent the degree of overflow, thereby providing a set of values corresponding to underflow numbers.

8. The method as recited in claim 7 wherein said set of provided values creates a symmetric number range resulting in a gradual loss of accuracy for overflow.

9. The method as recited in claim 1 wherein said step of converting the memory register representation further comprises the step of transcribing the memory sign portion to the floating-point sign portion.

10. The method as recited in claim 1 wherein said step of converting the memory register representation further comprises the step of extending the exponent portion.

11. The method as recited in claim 1 further comprising the steps of:

measuring the memory register mantissa portion for an underflow/overflow value, the underflow/overflow value being located on the right or least significant end of the mantissa portion and comprised of zero or more zero bits and a terminating one bit; and

adjusting the memory exponent portion based upon the size of said underflow/overflow value, the underflow value being subtracted from the exponent portion and the overflow value being added to the exponent portion.

12. The method as recited in claim 11 further comprising the steps of setting bits of the floating-point register value based upon the value of said adjusted memory exponent portion.

13. The method as recited in claim 1 wherein said step of converting the memory register representation further comprises the step of testing the memory sign portion, memory exponent portion, and memory mantissa portion to determine the state of the memory register representation.

14. The method as recited in claim 13 further comprising the step of setting bits of the floating-point register representation based upon said state of the memory register representation.

15. The method as recited in claim 1 further comprising the step of designating by arithmetic unit accuracy control logic an accuracy required of the converted floating-point number.

16. The method as recited in claim 1 further comprising the step of designating by arithmetic unit rounding control logic a rounding choice required of the converted floating-point number.

17. The method as recited in claim 16 wherein said rounding choice further comprises modifying bits to the right of an accuracy field of the mantissa portion.

18. The method as recited in claim 1 wherein said arithmetic computation further comprises the steps of chopping the resulting computed floating-point value to fit the mantissa portion;

and postponing said chopping until storing to memory thereby computing with maximal precision.

19. The method as recited in claim 1 wherein said step of converting the resulting floating-point register value further comprises the steps of:

testing the floating-point register exponent portion for underflow and overflow;

and inserting said underflow and overflow value into the memory mantissa portion.

20. The method as recited in claim 1 wherein said step of converting the resulting floating-point register value further comprises encoding an accuracy value of the floating-point register representation into the memory mantissa portion.

21. A method for processing floating-point numbers from memory register format to arithmetic unit register format and back, each floating-point number having at least a sign portion, an exponent portion and a mantissa portion, comprising the steps of:

selecting a primary load control mode for a memory register floating-point number to be converted;

testing for a memory value state by accessing bit statuses of the sign portion, exponent portion and mantissa portion of the memory register floating-point number;

converting as required by said primary load control mode the result of said testing of the memory value state into the arithmetic unit register;

selecting a primary arithmetic control mode for an arithmetic register floating-point number to be computed upon;

rounding the arithmetic register floating-point number as required by said primary arithmetic control mode;

performing an arithmetic operation upon the rounded arithmetic register floating-point number;

selecting a primary store control mode for said arithmetic register floating-point number to be converted;

testing the exponent portion of the arithmetic register floating-point number; and

converting as required by said primary store control mode the result of said testing of the exponent portion into the memory register.

22. An apparatus for processing floating-point numbers comprising:

means for converting a floating-point value from a random access memory register to

a floating-point unit register;

means for selecting an accuracy required of the converted value;

means for selecting a rounding choice required of the converted floating-point value;

means for performing an arithmetic operation upon at least one converted floating-point value based upon said selected accuracy and rounding;

means for chopping the result of the arithmetic operation to fit a mantissa portion of a floating-point value; and

means for converting the resulting floating-point value from the floating-point register representation to the random access memory representation.

23. The apparatus as recited in claim 22 further comprising a means for controlling the type of floating-point number to be converted from the random access memory register to the floating-point unit register.

24. The apparatus as recited in claim 22 further comprising a means for controlling the type of floating-point number to be converted from the floating-point unit register to the random access memory register.

25. An apparatus for processing one or more floating-point numbers from memory register format to arithmetic unit register format and back comprising:

one or more priority decoder circuits for converting said floating-point number to be loaded from a random access memory register to a floating-point unit register;

one or more masking circuits for setting the bits of said floating-point numbers from the random access memory register to the floating-point unit register;

one or more priority encoder circuits for rounding said floating-point number to be operated upon in said arithmetic logic unit;

an arithmetic logic unit for performing arithmetic operations upon the floating-point register numbers;

one or more priority encoder circuit for converting and encoding said floating-point number to be stored from the floating-point unit register to the random access memory register; and

one or more masking circuit for setting the bits or said floating-point numbers from the floating-point unit register to the random access memory register.

26. The apparatus as recited in claim 25 further comprising a test circuit for testing a floating-point unit register floating-point number for underflow and overflow.

27. The apparatus as recited in claim 26 further comprising an encoder circuit for converting the test result into a reverse comma code into the random access memory register.

28. The apparatus as recited in claim 25 further comprising an encoder circuit for converting an accuracy value into the random access memory register.