Apparatus and method for observing the mode of a memory device

• US 5,892,777 A
• Filed: 05/05/1997
• Issued: 04/06/1999
• Est. Priority Date: 05/05/1997
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Nesheiwat, Michael, Grass, Roger, O'Donnell, Arthur
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/851,287
• Time in Patent Office: 701 Days
• Field of Search: 371/21.1, 371/25.1, 371/37.6, 371/40.4, 371/67.1, 371/21.2, 371/27.5, 371/27.6, 395/430, 395/481, 395/183.13, 395/184.01, 395/183.06, 395/183.12, 365/201, 365/189.02, 365/189.01, 365/230.02, 365/230.08, 365/189.03, 365/189.05
• US Class Current: 714/718
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A method and apparatus observes a mode register (102) in a synchronous memory device. A multiplexer (306) selects the value of the mode register (102) or the conventional data path of the memory array (302) through the output buffer. The invention outputs the stored value of the control register (102) on output pins, such as address pins when no signal is expected. The multiplexer (306) maybe responsive to a variety of control signals.

Claims

1. A method for observing a control register in a memory device, the control register defining an operation of the memory device, the control register not observable from the memory device, the method comprising the steps of:

storing a received value in the control register responsive to a first signal;

outputting the received value responsive to a second control signal when no output is expected from the memory device; and

disabling the operation of the memory device responsive to the second control signal subsequent to the step of outputting.

2. The method of claim 1 wherein the step of outputting the received value further comprises the step of:

switching between an output of a memory array and the received value responsive to a first control signal.

3. The method of claim 1 wherein the step of outputting comprises the step of outputting the contents of a mode register of a synchronous DRAM.

4. The method of claim 1 wherein the step of storing the received value further comprises the step of:

transferring the received value to a second register responsive to the first signal.

5. The method of claim 4 further comprising the step of:

initializing the second register to a default value of all ones.

6. An apparatus for observing a mode of a memory device comprising:

a multiplexer selectively outputting either a first input or a second input responsive to a first control signal;

a first register storing a first value defining an operation of the memory device, the first register generating the first input;

a memory array storing a plurality of data bits responsive to received addresses, the memory array generating the second input; and

control logic generating the first control signal responsive to a received signal indicative of a power down command, the control logic generating the first control signal when no output is expected from the memory device.

7. The apparatus of claim 6 further comprising:

a second register for storing the first value responsive to a second control signal.

8. The apparatus of claim 7 wherein the control logic initializes the second register to a default value.

9. The apparatus of claim 6 wherein the memory device is a synchronous dynamic random access memory (SDRAM).

10. An apparatus for observing a mode of a memory device comprising:

a gating means for selectively outputting either a first input or a second input responsive to a first control signal;

a register storing a value defining an operation of the memory device, the register generating the first input;

storage means for storing a plurality of data bits responsive to received addresses, the storage means generating the second input; and

control logic generating the first control signal responsive to a predetermined value of the register.

11. The apparatus of claim 10 further comprising:

a second register for storing the first input responsive to a second control signal.

12. The apparatus of claim 11 wherein the control logic initializes the second register to a default value.

13. The apparatus of claim 11 wherein the gating means transmits the first input responsive to the second control signal.

14. The apparatus of claim 10 wherein the gating means transmits the first input responsive to a predetermined test mode.

15. The apparatus of claim 10 wherein the memory device is a synchronous dynamic random access memory (SDRAM).