Computer activity monitor providing idle thread and other event sensitive clock and power control

CAFC
  • US 5,892,959 A
  • Filed: 12/17/1996
  • Issued: 04/06/1999
  • Est. Priority Date: 06/01/1990
  • Status: Expired due to Term
First Claim
Patent Images

1. A power management system for use in a computer system comprising a plurality of computer system devices including a CPU device, a plurality of peripheral devices, a memory device, and a system bus which directly connects the CPU device with the peripheral devices, said computer system adapted to perform a plurality of activities, wherein said power management system comprises:

  • means for identifying each of said plurality of activities as either an active activity or an idle activity and for associating each of said plurality of activities with a predetermined activity value and with either it first arithmetic sign for activities identified as active activities or with a second arithmetic sign opposite to said first sign for activities identified as idle activities; and

    an activity monitor comprising;

    an activity count accumulator for accumulating an activity count upon the occurrence of each of said plurality of activities including;

    means for adding to a stored activity count, upon the occurrence of any one of said plurality of activities, a predetermined activity value associated with said particular activity; and

    means for comparing the accumulated stored activity count with a conserve threshold and for causing a CONSERVE signal if the accumulated activity count has a predetermined algebraic relationship relative to the conserve threshold; and

    a power control circuit coupled to said activity monitor which in response to the CONSERVE signal transitions from an ON state to a REDUCED state in which the power consumption of the computer is reduced relative to the power consumption in the ON state;

    wherein the power control circuit comprises a clock switching circuit and wherein;

    the clock switching circuit couples the CPU device to a clocking signal of a first frequency in the ON state; and

    the clock switching circuit provides to the CPU a clocking signal of a second frequency in the REDUCED state.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×