Semiconductor memory device with redundancy circuit

  • US 5,894,441 A
  • Filed: 03/31/1998
  • Issued: 04/13/1999
  • Est. Priority Date: 03/31/1997
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device comprising, a plurality of column selection lines, at least one redundant column selection line, a column decoder for activating one of said plurality of column selection lines in response to a column address, a first circuit generating a detection signal when the column address of a defective column selection line is supplied, and a second circuit activating said redundant column selection line in response to said detection signal and at least a part of said row address.

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