Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer

• US 5,895,957 A
• Filed: 01/03/1997
• Issued: 04/20/1999
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): FAHMY, WAEL M
• Application Number:
  US08/778,669
• Time in Patent Office: 837 Days
• Field of Search: 257/57, 257/66, 257/64, 257/65, 257/69, 257/347, 257/348, 257/349, 257/350, 257/351, 257/352, 257/353, 257/354
• US Class Current: 257/352
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element

Abstract

A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.

Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.

Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. |V_tn |=|V_tp |).

Claims

1. A transistor formed in an intrinsic silicon layer on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2, said transistor made by the process comprising the steps of;

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

selecting an areal portion of said silicon on sapphire and maintaining said areal portion at or below a temperature of approximately zero degrees centigrade (0°

C.) such that the temperature throughout said areal portion is substantially uniform during said ion implanting step;

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and

controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°

C. during any annealing and/or processing procedures performed subsequent to said ion implanting step which expose said layer of silicon to a non-oxidizing ambient environment, thereby maintaining an areal density of electrically active states in regions of said silicon layer not intentionally doped which is less than approximately 5×

10¹¹ cm^-2.

2. A transistor made by the process defined in claim 1 further comprising the step of forming a channel region in said layer of silicon which is intentionally doped to adjust a threshold voltage of said transistor.

3. A transistor made by the process defined in claim 1 wherein said transistor is a MOSFET.